Texas Instruments MSP50C614 manual Comparator

Comparator

The comparator, along with all of its associated functions, is enabled by setting bit 15 of the interrupt/general control register (IntGenCtrl, address 0x38). The default value of the register is zero: comparator disabled.

Note: IntGenCtrl Register Bit 15

At the time that bit 15 in the IntGenCtrl is set, PD4 and PD5 become the comparator inputs. At any time during which bit 15 is set, PD4 and PD5 MUST be set to INPUT (I/O Port D Control, address 0x1C, bits 4 and 5 CLEARed). Failure to do so may result in a bus contention.

The function of pins PD4 and PD5, and the behavior of events COND2, INT6, INT7, and TIMER1 are very different, depending on whether the comparator has been enabled or disabled. A summary of the various states appears in the following table:

Comparator ENABLED SET bit 15 in the IntGenCtrl, address 0x38 . . .

PD4 functions as comparator negative input PD5 functions as comparator positive input

COND2 maps to the state of the comparator

INT6 is triggered by a rising edge at PD5 INT7 is triggered by a falling edge at PD5

TIMER1 may be started by a falling edge at PD5 TIMER1 will be stopped by a rising edge at PD5

(port D Control, 0x1C, bit 4 MUST be 0) (port D Control, 0x1C, bit 5 MUST be 0)

(PD5 relative to PD4)

(relative to PD4)

(assuming TIMER1 Enable is 0)

Comparator DISABLED	CLEAR bit 15 in the IntGenCtrl, address 0x38 . . .
PD4 functions as a general I/O pin		(port D Control	0x1C,	bit 4 = 0 or 1)
PD5 functions as a general I/O pin		(port D Control	0x1C,	bit 5 = 0 or 1)
COND2 maps to the state of the I/O pin PD1		(0 or 1 logical)
INT6 is triggered by a rising edge at PD4		(0 to 1 logical)
INT7 is triggered by a falling edge at PD5		(1 to 0 logical)

TIMER1 is started/stopped in software by setting/clearing TIMER1 enable (IntGenCtrl)

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