Texas Instruments MSP50C614 manual Timer Registers

Timer Registers

In addition to being individually enabled, all interrupts must be GLOBALLY enabled before any one can be serviced. Whenever interrupts are globally disabled, the interrupt flag register may still receive updates on pending trigger events. Those trigger events, however, are not serviced until the next INTE instruction is encountered.

After an interrupt service branch, it is the responsibility of the programmer to re-SET the global interrupt enable, using the INTE instruction.

2.8 Timer Registers

The C614 contains two identical timers, TIMER1 and TIMER2. Each includes a period register and a count-down register. The period register (PRD1 or PRD2) defines the initial value for the counter, and the count-down register (TIM1 or TIM2) does the counting. When the count-down register decrements to the value 0x0000, then the value currently stored in the period register is loaded to the count-down register. The count-down register then resumes counting again from that value.

For each TIMER, there is an interrupt-trigger event associated with the TIMER's underflow condition (the point of reaching 0x0000 and then re-setting again). When enabled, the interrupt INT1 is triggered by the underflow of TIMER1, and the interrupt INT2 is triggered by the underflow of TIMER2. INT1 and INT2 are the second and third-highest priority interrupts in the C614. Refer to Section 2.7, Interrupt Logic, for a summary of the interrupt logic, and to Section 2.6.3, Interrupt Vectors, for a listing of the interrupt vectors.

Both the period and the count-down registers are readable and writeable as port-addressed registers:

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