Texas Instruments MSP50C614 manual ±2. Summary of C614s Peripheral Communications Ports, Reset LOW

Memory Organization: RAM and ROM

When writing to any of the locations in the I/O address map, therefore, the bit-masking need only extend as far as width of location. Within a 16-bit accumulator, the desired bits (width of location) should be right-justified. The write operation is accomplished using the OUT instruction, with the address of the I/O port as an argument.

A read from these locations is accomplished using the IN instruction, with the address of the I/O port as an argument. When reading from the I/O port to a 16-bit accumulator, the IN instruction automatically clears any extra bits in excess of width of location. The desired bits in the result will be right-justified within the accumulator.

Allowable access indicates whether the port is bidirectional, read-only, or write-only. The last column of the table points to the section in this manual where the functions of each bit have been defined in more detail.

Table 2±2. Summary of C614's Peripheral Communications Ports

I/O Map	Width of	Allowable	Control Register	Abbreviation	State after	Section for
Address	Location	Access	Name		RESET LOW	Reference
0x00	8 bits	read & write	I/O port A data	PA0..7 Data	unknown²
0x04	8 bits	read & write	I/O port A control	PA0..7 Ctrl	0x00 ³
0x08	8 bits	read & write	I/O port B data	PB0..7 Data	unknown
0x0C	8 bits	read & write	I/O port B control	PB0..7 Ctrl	0x00
0x10	8 bits	read & write	I/O port C data	PC0..7 Data	unknown	3.1.1
0x14	8 bits	read & write	I/O port C control	PC0..7 Ctrl	0x00
0x18	8 bits	read & write	I/O port D data	PD0..7 Data	unknown
0x1C	8 bits	read & write	I/O port D control	PD0..7 Ctrl	0x00
0x20	8 bits	read & write	I/O port E data	PE0..7 Data	unknown
0x24	8 bits	read & write	I/O port E control	PE0..7 Ctrl	0x00
0x28	8 bits	READ only	Input port F data	PF0..7 Data	unknown	3.1.2
0x2C	16 bits	read & write	Output port G data	PG0..15 Data	0x0000	3.1.3
0x30	16 bits	WRITE only	DAC data	DAC Data	0x0000	3.2.2
0x34	4 bits	read & write	DAC control	DAC Ctrl	0x0	3.2.2
0x38	16 bits	read & write	Interrupt/general Ctrl	IntGenCtrl	0x0000	3.4
0x39	8 bits	read & write	Interrupt flag	IFR	Same state as	2.7
					before RESET

² Input states are provided by the external hardware.

³A control register value of 0x00 yields a port configuration of all inputs.

MSP50C614 Architecture 2-17