Texas Instruments MSP50C614 manual Data Memory Address Unit

Data Memory Address Unit

For some instructions, the 5-bit string processor can also preincrement or predecrement the AP pointer-value by +1 or ±1, before being used by the accumulator register block. This utility can be effectively used to minimize software overhead in manipulating the accumulator address. The premodification of the address avoids the software pipelining effect that post-modification would cause.

Some C614 instructions reference only the accumulator register and cannot use or modify the offset register that is fetched at the same time. Other instruc- tions provide a selection field in the instruction word (A~ or ~A op-code bit). This has the effect of exchanging the column addressing sense and thus the source or order of the two registers. Also, some instructions can direct the ALU output to be written either to the accumulator register or to the offset accumula- tor register. Refer to Chapter 4, Instructions, for more details.

The ALU's accumulator block functions as a small workspace, which elimi- nates the need for many intermediate transfers to and from memory. This al- leviates the memory thrashing which frequently occurs with single accumula- tor designs.

2.3 Data Memory Address Unit

The data memory address unit (DMAU) provides addressing for data memory (internal RAM). The block diagram of the DMAU is shown in Figure 2±6. The unit consists of a dedicated arithmetic block and eight read/write registers (R0 through R7). Each read/write register is 16-bits in size. The arithmetic block is used to add, subtract, and compare memory-address operands. The register set includes four general-purpose registers (R0 to R3) and four special-purpose registers. The special-purpose registers are: the LOOP control register (R4), the INDEX register (R5), the PAGE register (R6), and the STACK register (R7). The DMAU generates a RAM address as output. The DMAU functions completely in parallel with the computational unit, which helps the C614 maintain a high computational throughput.

MSP50C614 Architecture 2-11