Texas Instruments MSP50C614 manual Program Counter Unit, Bit Logic Unit

Program Counter Unit

2.4 Program Counter Unit

The program counter unit provides addressing for program memory (onboard ROM). It includes a 16-bit arithmetic block for incrementing and loading addresses. It also consists of the program counter (PC), the data pointer (DP), a buffer register, a code protection write-only register, and a hardware loop counter (for strings and repeated-instruction loops). The program counter unit generates a ROM address as output.

The program counter value, PC, is automatically saved to the stack on various CALL instructions and interrupt service branches. The stack consists of one hardware-level register (TOS) which points to the top-of-stack. The TOS is followed by a software stack. The software stack resides in RAM and is addressed using the STACK register (R7) in indirect mode (see Section 2.3, Data Memory Address Unit).

The hardware loop counter controls the execution of repeated instructions using one of two modes: 1) consecutive iterations of a single instruction following the repeat (RPT) instruction, or 2) a single instruction which operates on a string of data values (string loops). For all types of repeated execution, interrupt service branches are automatically disabled (temporarily).

The data pointer (DP) register is loaded at two instances: 1) from the accumulator during lookup-table instructions, and 2) from the databus during the fetch of long string constants. To simplify algorithms which require sequential indices to lookup tables, the DP register may be stored in RAM.

2.5 Bit Logic Unit

The bit logic unit is a 1-bit unit which operates on flag bit data. It is controllable by eleven different instructions, which generate the decision flags for conditional program control. The results of operations performed by the bit logic unit are sent either to the flag bit of RAM memory or to the TF1 and TF2 bits of the status register (STAT).

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