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Texas Instruments MSP50C614 manual Class 8 Instructions Logic and Bit

Models: MSP50C614

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Instruction Classification

Table 4±31. Class 7 Instruction Encoding and Description (Continued)

		cc			cc names			Description

					cc name		Not cc name
					cc name		Not cc name

1	0	1	0	1				Unconditional

1	0	1	1	0				Not assigned

1	0	1	1	1				Not assigned

1	1	0	0	0	XZ		XNZ	Conditional on XSF

1	1	0	0	1	XS		XNS	Conditional on XZF

1	1	0	1	0	XG		XNG	Conditional on ! XSF and ! XZF

1	1	0	1	1				Not assigned

1	1	1	0	0				Not assigned

1	1	1	0	1				Not assigned

1	1	1	1	0				Not assigned

1	1	1	1	1				Not assigned

4.4.8Class 8 Instructions: Logic and Bit

This class of instructions provides a flexible and efficient means to make complex logical decisions. Instead of making a sequence of single bit decisions and constructing a logical statement through a branch decision tree, the program can sequentially combine several status conditions to directly construct a final logic value (TF1 or TF2) which can be used to control a subsequent branch or call. This class includes two subclasses. Class 8a instructions update one of the test flags (TF1 or TF2) with a logical combination of the old test flag value and an addressed memory flag value. Subclass 8b provides a flexible means of logically combining the test flag (TF1 or TF2) with a status condition and storing the results back to the test flag.

Table 4±32. Class 8a Instruction Encoding

Bit	16	15	14	13	12	11	10	9	8	7	6	5	4	3		2	1	0

Class 8a	1	0	0	1	1	flg	Not		C8a				flagadrs

Class 8b	1	0	0	1	0	flg	Not			cc				Rx			C8b

RFLAG {flagadrs}	1	0	0	1	1	0	0	0	1	1			flagadrs

SFLAG {flagadrs}	1	0	0	1	1	1	0	1	0	1			flagadrs

Assembly Language Instructions

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Texas Instruments MSP50C614 manual Class 8 Instructions Logic and Bit, ±32. Class 8a Instruction Encoding

Contents

MSP50C614 Mixed-Signal Processor Users Guide Important Notice About This Manual How to Use This ManualNotational Conventions This document uses the following conventionsThis provides three choices *, *+, or *± Csr ±a /user/ti/simuboard/utilitiesNotational Conventions Trademarks Information About Cautions and WarningsThis book may contain cautions and warnings Information About Cautions and WarningsPage Contents Contents Assembly Language InstructionsCode Development Tools ContentsixApplications ROM Usage With Respect to Various Synthesis AlgorithmsCustomer Information Contentsxi Figures ±11 ±10±12 ±13Tables ±33 ±32±34 ±35Page Introduction to the MSP50C614 Features of the C614 Features of the C614Applications ApplicationsIntroduction to the MSP50C614 Development Device MSP50P614 Development Device MSP50P614Functional Description Functional DescriptionC605 and C604 Preliminary Information C605 and C604 Preliminary Information±1. Functional Block Diagram for the C614 Resistor Trim Operation Connections Crystal Oscillator Operation Connections±3. Reset Circuit ±1. Signal and Pad Descriptions for the C614 Terminal Assignments and Signal DescriptionsTerminal Assignments and Signal Descriptions Description Pin # ±2. MSP50C614 100-Pin PJM Plastic Package Pinout DescriptionPD0 PD1 PD2 PD3 PD4 PD5 PD6 ±5 Pin Grid Array Package for the Development Device, P614 VPP VSS VDD DAC M DAC P MSP50C614 Architecture Architecture Overview MSP50C614 Architecture ±1. MSP50C614 Core Processor Block DiagramALU Multiplier Computation Unit±1. Signed and Unsigned Integer Representation Computation UnitComputation Unit Arithmetic Logic Unit ±3. Overview of the Multiplier Unit OperationAccumulator Block ±4. Overview of the Arithmetic Logic Unit AC0 . . . AC31 Accumulator BlockAccumulator Block Pointers AP0 . . . AP3Data Memory Address Unit Data Memory Address Unit±6. Data Memory Address Unit RAM ConfigurationData Memory Addressing Modes Bit Logic Unit Program Counter UnitProgram Counter Unit Memory Map Memory Organization RAM and ROMMemory Organization RAM and ROM Peripheral Communications Ports ±7. C614 Memory Map not drawn to scale±2. Summary of C614s Peripheral Communications Ports Reset LOWInterrupt Name ROM address Event Source Interrupt Priority Interrupt VectorsROM Code Security Write only Block Protection WordProtection marker = the value programmed at TM5… TM0 true≡ the binary complement of NTM = the value programmed at FM5… FM0 falseMacro Call Vectors Interrupt LogicInterrupt Logic IFR Interrupt Logic ±8. Interrupt Initialization Sequence Timer Registers Timer RegistersTriggers INT1 on underflow Timer Registers Oscillator Options Clock ControlPLL Performance Clock ControlClock Speed Control Register ±9. PLL PerformanceClkSpdCtrl register CPURtrim Register Read Only Applies to MSP50C614 Device Only RTO Oscillator Trim AdjustmentClkSpdCtrl Value Copied Shaded Execution Timing Execution TimingReduced Power Modes Reduced Power ModesReduced Power Modes Reduced Power Modes Light MID Deep ±3. Programmable Bits Needed to Control Reduced Power ModesComponent Determined → deeper sleep … relatively less power →By Controls Deeper sleep … Relatively less power → Event Determined Global interrupt enable is SET Peripheral Functions General-Purpose I/O Ports I/OPort a Port B Port C Port D Port E Peripheral Functions Input Port F Dedicated Input Port FTotem-Pole Output Port G Dedicated Output Port GInternal and External Interrupts Branch on D PortInterrupt Vector Source Trigger Event Priority Comment ±1. InterruptsPulse-Density Modulation Rate Digital-to-Analog Converter DACDAC Control and Data Registers Digital-to-Analog Converter DACOverflow bits Least-significant data value Ignored bits ±1. PDM Clock Divider PDM Clock DividerDigital-to-Analog Converter DAC CPU Pllm Comparator TIMER1 starts counting For INT7 is enabledCleared. Refer to .7, Interrupt Logic, for more details AddressComparator Interrupt/General Control Register Interrupt/General Control RegisterIntGenCtrl register Interrupt/General Control Register Hardware Initialization States Hardware Initialization StatesHardware Initialization States RZF Bit Bit Name Initialized Value DescriptionPage Assembly Language Instructions System Registers IntroductionTop of Stack, TOS Assembly Language InstructionsSystem Registers Product Low Register PL Product High Register PHAccumulators AC0±AC31 Indirect Register R0±R7 Accumulator Pointers AP0±AP3Bit Status Register Stat String Register STRFunction ±1. Status Register Stat1 MSP50P614/MSP50C614 Instruction Syntax Instruction Syntax and Addressing ModesAddressing Modes ±2. Addressing Mode EncodingOpcode Next a±3. Rx Bit Description ±4. Addressing Mode Bits and adrs Field Description±6. Auto Increment and Auto Decrement Modes ±5. MSP50P614/MSP50C614 Addressing Modes SummaryFlag Repeat Flag addressing mode encoding, flagadrsFlagadrs Clocks Words Addressing Operation, ² SyntaxSyntax Immediate AddressingExample MOV *0x012F * 2, *A0 Direct AddressingMulr *0x02A1 ±9. Indirect Addressing Syntax Indirect AddressingSyntaxOperation MOV A2, *R0 Relative Addressing*R4++ Movb *R7++, A3Short Relative A0, *R3+R5Long Relative MOV A3, *R6+0x10TF1, *0x20 Flag AddressingOr TF2, *R6+0x02 XOR TF1, *R6+0x208 Tag/Flag Bits TF1,*ram1 TF1 bit in Stat is set!? Possible sources of confusion Consider the following codeSymbol Explanation ±10. Symbols and ExplanationInstruction Classification Instruction Classification±11. Instruction Classification ±11. Symbols and ExplanationClass Sub- Description Class Sub Description Class 1 Instructions Memory and Accumulator Reference ±12. Classes and Opcode Definition±14. Class 1a Instruction Description ±13. Class 1 Instruction EncodingC1a ~A~ C1bC1b Mnemonic Description ±15. Class 1b Instruction DescriptionShltpls a n, adrs Class 2 Instructions Accumulator and Constant Reference±17. Class 2a Instruction Description ±16. Class 2 Instruction EncodingC2a Mnemonic Description Class 3 Instruction Accumulator Reference ±18. Class 2b Instruction DescriptionC2b Mnemonic Description ADD An ~, An ~, imm16 , next a±20. Class 3 Instruction Description ±19. Class 3 Instruction EncodingMnemonic Description Zero or be set equal to the sign bit Xsgm dependent MOV SV, An~ , next a ±21. Class 4a Instruction Encoding Class 4 Instructions Address Register and Memory Reference±23. Class 4b Instruction Description ±22. Class 4a Instruction Description±24. Class 4c Instruction Description ±25. Class 4d Instruction Description±26. Class 5 Instruction Encoding Class 5 Instructions Memory Reference±27. Class 5 Instruction Description RET² ±28. Class 6a Instruction Encoding Class 6 Instructions Port and Memory Reference±29. Class 6a Instruction Description C6a Mnemonic DescriptionClass 7 Instructions Program Control ±30. Class 6b Instruction DescriptionC6b Mnemonic Description Vector8 ±31. Class 7 Instruction Encoding and DescriptionJcc Ccc±32. Class 8a Instruction Encoding Class 8 Instructions Logic and Bit±34. Class 8b Instruction Description ±33. Class 8a Instruction DescriptionClass 9 Instructions Miscellaneous C8a Mnemonic Description±36. Class 9a Instruction Description ±35. Class 9a Instruction Encoding±37. Class 9b Instruction Description C9a Mnemonic Description±38. Class 9c Instruction Description Bit, Byte, Word and String Addressing±39. Class 9d Instruction Description C9c Mnemonic Description±3. Data Memory Organization and Addressing ±40. Data Memory Address and Data Relationship Mode Address Used Data Order Rx Post modify ²Movb A0, *0x0003 MOV A0, *0x0004Which uses the absolute word memory address ±4. Data Memory ExampleRflag MSP50P614/MSP50C614 Computational Modes MSP50P614/MSP50C614 Computational Modes±41. MSP50P614/MSP50C614 Computational Modes Computational Setting Resetting Function Mode InstructionSXM Example 4.6.2 Sovm Example 4.6.1 SovmExample 4.6.1 SXM Hardware Loop Instructions Hardware Loop InstructionsSyntax Operation Limitations ±42. Hardware Loops in MSP50P614/MSP50C614±43. Initial Processor State for String Instructions String InstructionsString Instructions Registers register# = valueMulapl A0, A0~ ±44. Lookup Instructions Lookup InstructionsLookup Instructions Instructions Description Data TransferMOV An, adrs SUB An MOV An, *An Special Filter Instructions Input/Output InstructionsInput/Output Instructions Xk±2 Xk+2 Xk±1 xk+1 32 or Yk = Σm =0..N hm⋅xk-mSpecial Filter Instructions STR,N±2 STR,0 0x0104 After FIR/COR execution Important note about setting the Stat register Firkcoeffs Coeffarray Samplebuf address Coeffarray address FIRK/CORK only Program memory FIRK/CORKFIR/COR only = 0..N CoeffarraySamplebuf Coeffarray is stored Conditionals ConditionalsOperands Symbol Meaning≤ dma6 ≤ ≤ dma16 ≤ ≤ port4 ≤ ≤ port6 ≤Clk AdrsnDma n FlgPma n Offset nPort n ±45. Auto Increment and Decrement ±46. Addressing Mode Bits and adrs Field Description±47. Flag Addressing Syntax and BIts Individual Instruction Descriptions Individual Instruction DescriptionsExecution 14.1 ADD Add wordSee Also DescriptionPC PC + Flags Affected AddbOpcode Clock , clk Words , w Adds Add StringAdds A1, A1~, A1 14.4 Bitwise A3, *R4Ð± ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XorsTF2, *0x0020 Src byte PC PC + Andb Bitwise and ByteOF, SF, ZF, CF are set accordingly Clock , clk Word , wAnds A0, A0~, A0 Ands Bitwise and StringAnds A0, A0~, *R2 Clock, clk Word, wSave next instruction address PC + Begloop Begin LoopFlags Affected None Opcode Order to loop N timesCall Unconditional Subroutine Call TOS PC + TOSR7 + NOPTrue condition Not true condition ±48. Names for ccSyntax Alternate Syntax Description 0x2010 CALL, VCALL, RET, IretCTF1 CrnbeStat flags set by src ± src1 operation 14.10 CMP Compare Two WordsPC = PC + w CMPB, CMPS, Jcc, CccCMP R0, R5 CMP R2, 0xfe20Cmpb R3 Cmpb Compare Two BytesPC PC + w Flags Affected Cmps Compare Two StringsCmps A1~ Cmps A2, A2~3n R+2 14.13 COR Correlation Filter FunctionXeven = R xeven + R5 Xeven ++Sample data. During Cork execution, interrupt is queued Cork Correlation Filter FunctionAn, *Rx 3nR+2 Rxeven = Rxeven + R5Decrement R4 by n 1 or First address after Begloop Else Endloop End LoopArgument, it assumes n =1 BEGLOOP, InteAn~ , next a Extsgn Sign Extend WordCopy accumulator sign flag SF to all 16 bits of An~ Dest , modDest Extsgns Sign Extend StringExtsgn 2n R+2 14.18 FIR FIR Filter Function Coefficients in RAMAssembly Language Instructions 101 Be even. During Firk execution, interrupts are queued FirkRPT, FIR, COR, Cork Idle Halt Processor Assembly Language Instructions 103Stop processor clocks INS, OUT, Outs 14.21 Input From Port Into WordA2~, 0x3d IN, OUT, Outs 14.22 INS Input From Port Into StringIM is Stat bit Intd Interrupt DisableStat to INTE, IretAssembly Language Instructions 107 Inte Interrupt EnableINTD, Iret R7 R7 ± Iret Return From InterruptSee Also RET, CALL, C cc, INTE, Intd Description Return from interrupt. Pop top of stack to program counterPC PC + 14.26 Jcc Conditional Jumps110 If test condition is false, a NOP is executed JNZ See Also JMP, CALL, C cc ExampleJE 0x2010, R3++R5 JIN1 0x2010, R1±±Post±modify Rx if specified 14.27 JMP Unconditional JumpRCF and RZF affected by post±modification of Rx See Also Jcc, CALL, Ccc Example14.28 MOV Move Data Word From Source to Destination Clock, clk Word, w With RPT, clk Class XSF, XZF are set accordinglyTFn, cc , Rx STR, imm8116 With some operand types Example 4.14.28.10 MOV MR, A3, ±±A MOVU, MOVT, MOVB, MOVBS, MovsExample 4.14.28.11 MOV A1~, *A1 Example 4.14.28.12 MOV *0x0200 * 2, R0Example 4.14.28.15 MOV *0x0200 * 2, R0 Example 4.14.28.13 MOV R1, 0x0200Transfer R5 to R0 Example Example 4.14.28.18 MOV *R6 + 8 * 2, DPExecution + PH Movaph Move With Adding PHMOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs Execution An + PH Movaphs Move With Adding PHBackground. See .8 for more details MOVAPH, MOVTPH, MOVTPHS, MOVSPH, MovsphsCopy value of unsigned src byte to dest byte Movb Move Byte From Source to DestinationMovb A0, *R2 Copy data memory byte pointed by R2 to accumulator A0Movb A0, 0xf2 Movb *R2, A0Movb R2 TAG bit is set to bit 17 th value Movbs Move Byte String from Source to DestinationMovbs A2, *0x0200 Movbs *0x0200, A2Movs Move String from Source to Destination Movs A1, A1~ Movs A2~Movs A1~, A1 Movsph Assembly Language Instructions 127MOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs Movsphs Move String With Subtract From PH Second word ± PH MR contents of adrsDetails MOVSPH, MOVAPH, MOVAPHS, MOVTPH, MovtphsPC PC + w Flags Affected None Opcode MovtAvailable MOVU, MOV, MOVT, MOVB, MOVBS, MovsTAG bit is set accordingly UM is set to Movu Move Data UnsignedMOV, MOVB, MOVT, MOVBS, Movs Copy the value pointed by R3 to MRAssembly Language Instructions 131 MR * src PC PC + w Flags Affected 14.38 MUL Multiply RoundedAccumulator pointer if specified MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, MulaplMuls Multiply String With No Data Transfer Length nS+2, where nS is the value in STR registerPH,PL MR * src string MUL, MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MultplsPH ,PL MR * src Mulapl Multiply and Accumulate ResultBackground. See .8 for more detail MULAPLS, MULSPL, MULSPLS, MULTPL, MultplsMR * src Mulapls Multiply String and Accumulate ResultMULAPL, MULSPL, MULSPLS, MULTPL, Multpls Occuring in the background. See .8 for more details Mulspl Multiply and Subtract PL From AccumulatorMULSPLS, MULTPL, MULTPLS, MULAPL, Mulapls Syntax Description Mulspl adrsFrom dest string Mulspls Multiply String and Subtract PL From AccumulatorMULSPL, MULTPL, MULTPLS, MULAPL, Mulapls Syntax Description Mulspls adrsMultpl Multiply and Transfer PL to Accumulator Execution PH, PL MR * src PC PC + Flags Affected MultplsStored in An string MULTPL, MULAPL, MULAPLS, MULSPL, MulsplsAccumulator Negac Twos Complement Negation of AccumulatorNEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs Example 4.14.46.1 Negac A3~, A3, ±±ANegacs Twos Complement Negation of Accumulator String Assembly Language Instructions 141Dest accumulator string NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, NotacsExecution PC PC + 14.48 NOP No OperationRPT NOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, Xors Notac Ones Complement Negation of AccumulatorNEGAC, Negacs Example 4.14.49.1 Notac A3~, A3, ±±AAccumulator string Notacs Ones Complement Negation of Accumulator StringNegacs A3~TFn bits in Stat register are set accordingly 14.51 or Bitwise Logical orAccumulator pointers are allowed with some operand types Or A0, *R0++R5 ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NotacsOr TF1, *R6+0x22 Or src 14.52 ORB Bitwise or ByteAccumulator is affected OR, ORS, AND, ANDS, XOR, XORS, NOTAC, NotacsPC + w Flags Affected 14.53 ORS Bitwise or StringOR, ORB, AND, ANDS, XOR, XORS, NOTAC, Notacs ORS A0, A0~, A0Address is multipled by 4 to get the actual port address 14.54 OUTOUTS, IN, INS Port6 specified in the instruction Outs Output String to PortOUT, IN, INS Port6 , An ~14.56 RET Return From Subroutine CALL, Ccc Assembly Language Instructions 151PC TOS CALL, i.e., RET followed by a RET should not be allowedSflag , Stag , Rtag Rflag Reset Memory FlagExample 4.14.57.2 Rflag *R6 + Resets the fractional mode. Clears FM bit of Stat Reset Fractional Mode Syntax14.58 RFM STAT.FMSaturation output normal mode Rovm Reset Overflow ModeResets the overflow mode to zero Stat .OMLoad src to repeat counter 14.60 RPT Repeat Next InstructionLoad imm8 to repeat counter After execution completesStag , Rflag , Sflag Rtag Reset TagRtag *R6+0x0002 Rtag *R6+0x0003Assembly Language Instructions 157 14.62 RXM Reset Extended Sign ModeSTAT.XM SXMSflag Set Memory Flag Address flagadrs only accesses the 17 th bitRflag , Stag , Rtag Mode for signed fractional arithmetic 14.64 SFM Set Fractional ModeAssembly Language Instructions 159 Set fractional mode. Set FM bit of Stat toPH , PL 14.65 SHL Shift LeftAccumulator. Use Shlac for this purpose ShlsIts offset. LSB of result is set to zero Shlac Shift Left AccumulatorShift accumulator A1 by one bit to the left Example 4.14.66.2 Shlac A1~, A1, ±±AAccumulators in the string Shlacs Shift Left Accumulator String IndividuallyExample 4.14.68.1 Shlapl A0, *R4++R5 Shlapl Shift Left with AccumulateShlapl A2, *R1++ Example 4.14.68.3 Shlapl A1, A1, ++AShift data memory string left, add PL to a n Shlapls Shift Left String With AccumulateShift a n ~ string left, addb PL to a n ~ Shls Shift Left Accumulator String to Product Assembly Language Instructions 165Execution PH, PL An~Example 4.14.71.1 Shlspl A0, *R4++R5 Shlspl Shift Left With Subtract PLShlspl A2, *R1++ Example 4.14.71.3 Shlspl A1, A1, ++ABit to the next accumulator Shlspls Shift Left String With Subtract PLShlspl , Shltpl , SHLTPLS, SHLAPL, Shlapls Syntax Description Shlspls An, adrsExample 4.14.73.1 Shltpl A0, *R4++R5 Shltpl Shift Left and Transfer PL to AccumulatorShltpl A2, *R1++ Example 4.14.73.3 Shltpl A1, A1, ++AExecution PH, PL src SV Shltpls Shift Left String and Transfer PL to AccumulatorReceives the same data as PH SHLTPL, SHLAPL, SHLAPLS, SHLSPL, ShlsplsRegister Shrac Shift Accumulator RightShift right one bit the accumulator A1 Example 4.14.75.2 Shrac A1~, A1, ++AShracs Shift Accumulator String Right Assembly Language Instructions 171SHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, Shltpl ShltplsOutput DSP mode Set Overflow Mode SyntaxSovm STAT.OMRTAG, RFLAG, Sflag StagStag *0x401 Dest, src , src1 , next a 14.79 SUB SubtractAn ~ , An , adrs , next a An ~ , An ~ , imm16 , next aSUB A1, A1~, A1 Example 4.14.79.2 SUB A0, A0, 2, ++ASUB A3~, A3, *R4Ð SUB R3, R5Subtract 0x45 from accumulator A2 byte Subb Subtract ByteSubtract 0xF2 from register R3 byte Syntax Description Subb a n, imm8Subs Subtract Accumulataor String Assembly Language Instructions 177Subs A2, A2~, A2 Subs A2, A2, A2~Subs A3~, A3~, PH Sets extended sign mode status register Stat bit 0 to 14.82 SXM Set Extended Sign ModeAssembly Language Instructions 179 RXMPush PC + 0x7F00 Vcall Vectored CallR7 R7 + Flags Affected See Also RET, IRET, CALL, C cc ExampleXOR src For two operands 14.84 XOR Logical XORXOR src For three operands TAG bit is set accordingly Src is flagadrsExample 4.14.84.1 XOR A1, A1, 0x13FF XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NotacsExample 4.14.84.2 XOR A0, A0, 2, ++A Xorb Logical XOR Byte Assembly Language Instructions 183XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Dest string Xors Logical XOR StringXOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Xors A2, A2~, A2Assembly Language Instructions 185 Reset the content of accumulator A0 to zero14.87 ZAC Zero Accumulator ZacsZacs Zero Accumulator String Reset the content of offset accumulator string A1~ to zeroPC PC + Flags Affected ZF = Zero the specified accumulator stringInstruction Set Encoding Assembly Language Instructions 187Instruction Set Encoding 188 Assembly Language Instructions 189 190 Assembly Language Instructions 191 192 Assembly Language Instructions 193 194 True condition Not true condition Assembly Language Instructions 195Instruction Set Summary An~, An~ , next a Pma16 , Rmod Assembly Language Instructions 197An~, imm16 , next a Rx, R5~, adrs , next a ±46 Adrs, a n~ , next a ±46Adrs , *An ±46 An ~, imm16 , next aAdrs, SV Assembly Language Instructions 199Adrs, APn Adrs, TOS~ , next a MR, adrs~, a n~ , next a ~ , a n~TFn, flagadrs NR+3 TFn, cc , Rx An~, An~ , next a NR+3 Assembly Language Instructions 201An~, An~, pma16 An~, An~, An~, a n, a n~ , next a ~, a n~~, a n, a n~ ~, a n~, PHConditional on RZF=0 and RCF=1 Not condition RZF≠0 or RCF≠1 Conditional on RCF=1 Not condition RCF=0Conditional on RZF=1 Not condition RZF=0 Conditional on ZF=0 and SF=1 Not condition ZF≠0 or SF≠1Instruction Set Summay 204Assembly Language InstructionsMC = Pllm value+1 ⋅ 131.07 kHz 206Assembly Language Instructions Summay Instruction Set Summay 208Assembly Language Instructions Code Development Tools Introduction MSP50C6xx Software Development Tool MSP50C6xx Software Development ToolCode Development Tools PC Requirements RequirementsDevelopment Requirements RequirementsHardware Installation Hardware InstallationSoftware Installation Software Installation±5. Setup Window ±6. Exit Setup Dialog ±8. Choose Destination Location Dialog ±9. Select Program Folder Dialog ±10. Copying Files ±11.Setup Complete Dialog Open Screen Software EmulatorSoftware Emulator ±13. Project Menu Projects ±15. File Menu Options±16. MSP50P614/MSP50C614 Code Development Windows Description of Windows±17. RAM Window ±18. CPU Window ±19. Program Window ±20. Hardware Breakpoint Dialog ±21. Inspect Dialog Debugging a Program ±23. I/O Ports Window±24. Debug Menu Software Emulator ±25. Eprom Programming Dialog ±26. Trace Mode ±27. Init Menu Option Initializing ChipEmulator Options ±28. Options Menu Emulator Online Help System ±30. Windows Menu Options±31. Context Sensitive Help System Known Differences, Incompatibilities, Restrictions Assembler DLL AssemblerAssembler Examples Assembler Directives~ indicates bitwise complement #IFDEF #ELSE see #IF and #IFDEF#IFNDEF symbol Example #IFDEF symbol#ELSE #ENDIFAssembler Linker LinkerIerr=LINKMAIN sourcefile,exefile C± ± Compiler± ± Compiler Foreword External References Variable TypesType Name Mnemonic Range Size in Bytes Example 4 C± ± Directives Defines a replacement string for a given stringWithout Arguments With ArgumentsMust be present to terminate a #ifdef or #ifndef directive See #if directiveInclude Files Initializations Function Prototypes and DeclarationsRAM Usage String Functions±1. String Functions An example of the use of xferconst is Constant FunctionsComparisons Implementation DetailsThis section is C± ± specific Signed comparison of a and b. a is in A0, b is in A0~Unsigned comparison of a and b. a is in A0, b is in A0~ Assembly VectorFunction Calls DivisionStack frame has the following structure Low Address High AddressCmmfunc bidonint i1,char *i2 is valid, but Programming ExampleOn Call On RETIfteststringm2,0,lgm2,LTSN Programming Example, C ±± With Assembly Routines ±±±±±±±±±±±±±±± Addb R7,2 To C function return in cmmreturn ±±±±±±±±±±±±±± OldR5 Return Addr Param R7,R5 Stack data Param ±±±±±±±±±±±±±± To ASM function return External ProvidedData Iprtc Implementation Details Nop ret Dummy interrupt routines Implementation Details Implementation Details Reported Bugs With Code Development Tool Beware of Stack CorruptionBeware of Stack Corruption Page Applications Application Circuits Application CircuitsMSP50P614 only 100 kΩ MSP50C614/MSP50P614 Initialization Codes MSP50C614/MSP50P614 Initialization CodesFile init.asm Begloop ~,TIM2REFOSC + TIM2IMR Overview Texas Instruments C614 Synthesis CodeGetting Started Texas Instruments C614 Synthesis CodeDirectory Structure Running the ProgramSpkram.irx ROM File DescriptionAdding Another Module RAM UsageUnderstanding the RAM Map Modifying Files and ProjectsThese files may be edited for special purpose code Memory OverlayThese files should never be edited Creating a New ProjectROM Usage With Respect to Various Synthesis Algorithms ROM Usage With Respect to Various Synthesis AlgorithmsCustomer Information Die Bond-Out Coordinates Mechanical InformationMechanical Information Customer Information Package Information±1 -Pin PJM Mechanical Information ±2 -Pin Grid Array Package for the Development Device, P614 ±3 Pin Grid Array PGA Package Leads, P614 Customer Information Fields in the ROM Customer Information Fields in the ROMDevice Production Sequence Speech Development CycleSpeech Development Cycle Nprf Device Production SequenceNew Product Release Forms Ordering InformationOrdering Information 614New Product Release Forms Authorization to Generate MASKS, PROTOTYPES, and Risk UnitsPage MSP50C605 Preliminary Data Introduction Features ArchitectureArchitecture FeaturesPort Name IO Location MSP50C614 MSP50C605 1 RAM 3 I/O Pins2 ROM Port Description Function Name AddressFigure A±1. MSP50C605 Architecture Data Memory Program MemoryData ROM Peripheral PortsPlastic Package Description Pin# Page MSP50C604 Preliminary Data Introduction Features Architecture PackagingIntroduction MSP50C604 Preliminary Data ArchitectureFigure B±1. MSP50C604 Block Diagram Host Write Sequence Slave Mode OperationHost Read Sequence Data Memory Program MemoryPeripheral Ports Interrupts Packaging PackagingPlastic Package Packaging Topic MSP50C605 Data SheetMSP50C605 Data Sheet