Manuals / Texas Instruments / Home Audio / Stereo System

Texas Instruments MSP50C614 manual ±8. Interrupt Initialization Sequence

Models: MSP50C614

1 414

Download 414 pages 24.44 Kb

Page 55

Image 55

Interrupt Logic

Figure 2±8 provides an overview of the interrupt control sequence. INT0 is the highest priority interrupt, and INT7 is the lowest priority interrupt.

Figure 2±8. Interrupt Initialization Sequence

INTD	CLEAR
instruction
	SET



INTE
instruction

Interrupt

Service

Routine

(1 of 8)

INTE

IRET

Global Interrupt Enable

CLEAR

Interrupt-Trigger Event

•Internal Timer Underflow

•External Input Falling-Edge

•External Input Rising-Edge

•Software Write Instruction²

SET BIT

CLEAR BIT		INT Flag bits (IFR)
		Associated With the Interrupt-Trigger Event
		Associated With the Interrupt-Trigger Event
		Interrupt Flag Register (0x39)

INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0

INT Mask bits (IMR)

Specific Enable for Interrupt Service

Interrupt / General Control Register (0x38)²

INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0

Interrupt Service Branch

Highest Priority INT is Selected From

Among Those Flagged and Enabled.

Program Branches to Location

Stored in Interrupt Vector.

Interrupt Vector Storage

0x7FF0 0x7FF2 0x7FF4 0x7FF6 0x7FF1 0x7FF3 0x7FF5 0x7FF7

² The port-addressed write instruction (OUT) can be used to SET or CLEAR bits in the IFR and IMR.

MSP50C614 Architecture

2-25

Page 55

Image 55

Texas Instruments MSP50C614 manual ±8. Interrupt Initialization Sequence

Contents

MSP50C614 Mixed-Signal Processor Users Guide Important Notice This document uses the following conventions How to Use This ManualAbout This Manual Notational ConventionsThis provides three choices *, *+, or *± Csr ±a /user/ti/simuboard/utilitiesNotational Conventions Information About Cautions and Warnings Information About Cautions and WarningsTrademarks This book may contain cautions and warningsPage Contents Contents Assembly Language InstructionsCode Development Tools ContentsixApplications ROM Usage With Respect to Various Synthesis AlgorithmsCustomer Information Contentsxi Figures ±13 ±10±11 ±12Tables ±35 ±32±33 ±34Page Introduction to the MSP50C614 Features of the C614 Features of the C614Applications ApplicationsIntroduction to the MSP50C614 Development Device MSP50P614 Development Device MSP50P614Functional Description Functional DescriptionC605 and C604 Preliminary Information C605 and C604 Preliminary Information±1. Functional Block Diagram for the C614 Resistor Trim Operation Connections Crystal Oscillator Operation Connections±3. Reset Circuit ±1. Signal and Pad Descriptions for the C614 Terminal Assignments and Signal DescriptionsTerminal Assignments and Signal Descriptions Description Pin # ±2. MSP50C614 100-Pin PJM Plastic Package Pinout DescriptionPD0 PD1 PD2 PD3 PD4 PD5 PD6 ±5 Pin Grid Array Package for the Development Device, P614 VPP VSS VDD DAC M DAC P MSP50C614 Architecture Architecture Overview MSP50C614 Architecture ±1. MSP50C614 Core Processor Block DiagramALU Computation Unit Computation UnitMultiplier ±1. Signed and Unsigned Integer RepresentationComputation Unit Arithmetic Logic Unit ±3. Overview of the Multiplier Unit OperationAccumulator Block ±4. Overview of the Arithmetic Logic Unit AP0 . . . AP3 Accumulator BlockAC0 . . . AC31 Accumulator Block PointersData Memory Address Unit Data Memory Address Unit±6. Data Memory Address Unit RAM ConfigurationData Memory Addressing Modes Bit Logic Unit Program Counter UnitProgram Counter Unit Memory Map Memory Organization RAM and ROMMemory Organization RAM and ROM Peripheral Communications Ports ±7. C614 Memory Map not drawn to scale±2. Summary of C614s Peripheral Communications Ports Reset LOWInterrupt Name ROM address Event Source Interrupt Priority Interrupt VectorsROM Code Security Write only Block Protection Word= the value programmed at FM5… FM0 false = the value programmed at TM5… TM0 trueProtection marker ≡ the binary complement of NTMMacro Call Vectors Interrupt LogicInterrupt Logic IFR Interrupt Logic ±8. Interrupt Initialization Sequence Timer Registers Timer RegistersTriggers INT1 on underflow Timer Registers Clock Control Clock ControlOscillator Options PLL PerformanceClock Speed Control Register ±9. PLL PerformanceClkSpdCtrl register CPURtrim Register Read Only Applies to MSP50C614 Device Only RTO Oscillator Trim AdjustmentClkSpdCtrl Value Copied Shaded Execution Timing Execution TimingReduced Power Modes Reduced Power ModesReduced Power Modes Reduced Power Modes Light MID Deep ±3. Programmable Bits Needed to Control Reduced Power ModesComponent Determined → deeper sleep … relatively less power →By Controls Deeper sleep … Relatively less power → Event Determined Global interrupt enable is SET Peripheral Functions General-Purpose I/O Ports I/OPort a Port B Port C Port D Port E Peripheral Functions Input Port F Dedicated Input Port FTotem-Pole Output Port G Dedicated Output Port GInternal and External Interrupts Branch on D PortInterrupt Vector Source Trigger Event Priority Comment ±1. InterruptsDigital-to-Analog Converter DAC Digital-to-Analog Converter DACPulse-Density Modulation Rate DAC Control and Data RegistersOverflow bits Least-significant data value Ignored bits ±1. PDM Clock Divider PDM Clock DividerDigital-to-Analog Converter DAC CPU Pllm Comparator Address For INT7 is enabledTIMER1 starts counting Cleared. Refer to .7, Interrupt Logic, for more detailsComparator Interrupt/General Control Register Interrupt/General Control RegisterIntGenCtrl register Interrupt/General Control Register Hardware Initialization States Hardware Initialization StatesHardware Initialization States RZF Bit Bit Name Initialized Value DescriptionPage Assembly Language Instructions System Registers IntroductionTop of Stack, TOS Assembly Language InstructionsSystem Registers Product Low Register PL Product High Register PHAccumulators AC0±AC31 Indirect Register R0±R7 Accumulator Pointers AP0±AP3Bit Status Register Stat String Register STRFunction ±1. Status Register Stat1 MSP50P614/MSP50C614 Instruction Syntax Instruction Syntax and Addressing ModesNext a ±2. Addressing Mode EncodingAddressing Modes Opcode±3. Rx Bit Description ±4. Addressing Mode Bits and adrs Field Description±6. Auto Increment and Auto Decrement Modes ±5. MSP50P614/MSP50C614 Addressing Modes SummaryClocks Words Addressing Operation, ² Syntax Flag addressing mode encoding, flagadrsFlag Repeat FlagadrsSyntax Immediate AddressingExample MOV *0x012F * 2, *A0 Direct AddressingMulr *0x02A1 ±9. Indirect Addressing Syntax Indirect AddressingSyntaxOperation Movb *R7++, A3 Relative AddressingMOV A2, *R0 *R4++Short Relative A0, *R3+R5Long Relative MOV A3, *R6+0x10XOR TF1, *R6+0x20 Flag AddressingTF1, *0x20 Or TF2, *R6+0x028 Tag/Flag Bits TF1,*ram1 TF1 bit in Stat is set!? Possible sources of confusion Consider the following codeInstruction Classification ±10. Symbols and ExplanationSymbol Explanation Instruction Classification±11. Instruction Classification ±11. Symbols and ExplanationClass Sub- Description Class Sub Description Class 1 Instructions Memory and Accumulator Reference ±12. Classes and Opcode DefinitionC1b ±13. Class 1 Instruction Encoding±14. Class 1a Instruction Description C1a ~A~C1b Mnemonic Description ±15. Class 1b Instruction DescriptionShltpls a n, adrs Class 2 Instructions Accumulator and Constant Reference±17. Class 2a Instruction Description ±16. Class 2 Instruction EncodingC2a Mnemonic Description ADD An ~, An ~, imm16 , next a ±18. Class 2b Instruction DescriptionClass 3 Instruction Accumulator Reference C2b Mnemonic Description±20. Class 3 Instruction Description ±19. Class 3 Instruction EncodingMnemonic Description Zero or be set equal to the sign bit Xsgm dependent MOV SV, An~ , next a ±21. Class 4a Instruction Encoding Class 4 Instructions Address Register and Memory Reference±25. Class 4d Instruction Description ±22. Class 4a Instruction Description±23. Class 4b Instruction Description ±24. Class 4c Instruction Description±26. Class 5 Instruction Encoding Class 5 Instructions Memory Reference±27. Class 5 Instruction Description RET² C6a Mnemonic Description Class 6 Instructions Port and Memory Reference±28. Class 6a Instruction Encoding ±29. Class 6a Instruction DescriptionClass 7 Instructions Program Control ±30. Class 6b Instruction DescriptionC6b Mnemonic Description Ccc ±31. Class 7 Instruction Encoding and DescriptionVector8 Jcc±32. Class 8a Instruction Encoding Class 8 Instructions Logic and BitC8a Mnemonic Description ±33. Class 8a Instruction Description±34. Class 8b Instruction Description Class 9 Instructions MiscellaneousC9a Mnemonic Description ±35. Class 9a Instruction Encoding±36. Class 9a Instruction Description ±37. Class 9b Instruction DescriptionC9c Mnemonic Description Bit, Byte, Word and String Addressing±38. Class 9c Instruction Description ±39. Class 9d Instruction Description±3. Data Memory Organization and Addressing MOV A0, *0x0004 Mode Address Used Data Order Rx Post modify ²±40. Data Memory Address and Data Relationship Movb A0, *0x0003Which uses the absolute word memory address ±4. Data Memory ExampleRflag MSP50P614/MSP50C614 Computational Modes MSP50P614/MSP50C614 Computational Modes±41. MSP50P614/MSP50C614 Computational Modes Computational Setting Resetting Function Mode InstructionSXM Example 4.6.2 Sovm Example 4.6.1 SovmExample 4.6.1 SXM Hardware Loop Instructions Hardware Loop InstructionsSyntax Operation Limitations ±42. Hardware Loops in MSP50P614/MSP50C614Registers register# = value String Instructions±43. Initial Processor State for String Instructions String InstructionsMulapl A0, A0~ Instructions Description Data Transfer Lookup Instructions±44. Lookup Instructions Lookup InstructionsMOV An, adrs SUB An MOV An, *An Xk±2 Xk+2 Xk±1 xk+1 32 or Yk = Σm =0..N hm⋅xk-m Input/Output InstructionsSpecial Filter Instructions Input/Output InstructionsSpecial Filter Instructions STR,N±2 STR,0 0x0104 After FIR/COR execution Important note about setting the Stat register Firkcoeffs Coeffarray Coeffarray address FIRK/CORK only Program memory FIRK/CORKCoeffarray Samplebuf address FIR/COR only = 0..NSamplebuf Coeffarray is stored Conditionals Conditionals≤ port4 ≤ ≤ port6 ≤ Symbol MeaningOperands ≤ dma6 ≤ ≤ dma16 ≤Flg AdrsnClk Dma nPma n Offset nPort n ±45. Auto Increment and Decrement ±46. Addressing Mode Bits and adrs Field Description±47. Flag Addressing Syntax and BIts Individual Instruction Descriptions Individual Instruction DescriptionsExecution 14.1 ADD Add wordSee Also DescriptionPC PC + Flags Affected AddbOpcode Clock , clk Words , w Adds Add StringAdds A1, A1~, A1 14.4 Bitwise A3, *R4Ð± ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XorsTF2, *0x0020 Clock , clk Word , w Andb Bitwise and ByteSrc byte PC PC + OF, SF, ZF, CF are set accordinglyClock, clk Word, w Ands Bitwise and StringAnds A0, A0~, A0 Ands A0, A0~, *R2Order to loop N times Begloop Begin LoopSave next instruction address PC + Flags Affected None OpcodeCall Unconditional Subroutine Call NOP TOSTOS PC + R7 +True condition Not true condition ±48. Names for ccSyntax Alternate Syntax Description Crnbe CALL, VCALL, RET, Iret0x2010 CTF1CMPB, CMPS, Jcc, Ccc 14.10 CMP Compare Two WordsStat flags set by src ± src1 operation PC = PC + wCMP R0, R5 CMP R2, 0xfe20Cmpb R3 Cmpb Compare Two BytesCmps A2, A2~ Cmps Compare Two StringsPC PC + w Flags Affected Cmps A1~Xeven ++ 14.13 COR Correlation Filter Function3n R+2 Xeven = R xeven + R5Rxeven = Rxeven + R5 Cork Correlation Filter FunctionSample data. During Cork execution, interrupt is queued An, *Rx 3nR+2BEGLOOP, Inte Endloop End LoopDecrement R4 by n 1 or First address after Begloop Else Argument, it assumes n =1Dest , mod Extsgn Sign Extend WordAn~ , next a Copy accumulator sign flag SF to all 16 bits of An~Dest Extsgns Sign Extend StringExtsgn 2n R+2 14.18 FIR FIR Filter Function Coefficients in RAMAssembly Language Instructions 101 Be even. During Firk execution, interrupts are queued FirkRPT, FIR, COR, Cork Idle Halt Processor Assembly Language Instructions 103Stop processor clocks INS, OUT, Outs 14.21 Input From Port Into WordA2~, 0x3d IN, OUT, Outs 14.22 INS Input From Port Into StringINTE, Iret Intd Interrupt DisableIM is Stat bit Stat toAssembly Language Instructions 107 Inte Interrupt EnableINTD, Iret Return from interrupt. Pop top of stack to program counter Iret Return From InterruptR7 R7 ± See Also RET, CALL, C cc, INTE, Intd DescriptionPC PC + 14.26 Jcc Conditional Jumps110 If test condition is false, a NOP is executed JIN1 0x2010, R1±± See Also JMP, CALL, C cc ExampleJNZ JE 0x2010, R3++R5See Also Jcc, CALL, Ccc Example 14.27 JMP Unconditional JumpPost±modify Rx if specified RCF and RZF affected by post±modification of Rx14.28 MOV Move Data Word From Source to Destination STR, imm8 XSF, XZF are set accordinglyClock, clk Word, w With RPT, clk Class TFn, cc , Rx116 With some operand types Example 4.14.28.12 MOV *0x0200 * 2, R0 MOVU, MOVT, MOVB, MOVBS, MovsExample 4.14.28.10 MOV MR, A3, ±±A Example 4.14.28.11 MOV A1~, *A1Example 4.14.28.18 MOV *R6 + 8 * 2, DP Example 4.14.28.13 MOV R1, 0x0200Example 4.14.28.15 MOV *0x0200 * 2, R0 Transfer R5 to R0 ExampleExecution + PH Movaph Move With Adding PHMOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs MOVAPH, MOVTPH, MOVTPHS, MOVSPH, Movsphs Movaphs Move With Adding PHExecution An + PH Background. See .8 for more detailsCopy data memory byte pointed by R2 to accumulator A0 Movb Move Byte From Source to DestinationCopy value of unsigned src byte to dest byte Movb A0, *R2Movb A0, 0xf2 Movb *R2, A0Movb R2 Movbs *0x0200, A2 Movbs Move Byte String from Source to DestinationTAG bit is set to bit 17 th value Movbs A2, *0x0200Movs Move String from Source to Destination Movs A1, A1~ Movs A2~Movs A1~, A1 Movsph Assembly Language Instructions 127MOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs MOVSPH, MOVAPH, MOVAPHS, MOVTPH, Movtphs Second word ± PH MR contents of adrsMovsphs Move String With Subtract From PH DetailsMOVU, MOV, MOVT, MOVB, MOVBS, Movs MovtPC PC + w Flags Affected None Opcode AvailableCopy the value pointed by R3 to MR Movu Move Data UnsignedTAG bit is set accordingly UM is set to MOV, MOVB, MOVT, MOVBS, MovsAssembly Language Instructions 131 MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, Mulapl 14.38 MUL Multiply RoundedMR * src PC PC + w Flags Affected Accumulator pointer if specifiedMUL, MULR, MULAPL, MULSPL, MULSPLS, MULTPL, Multpls Length nS+2, where nS is the value in STR registerMuls Multiply String With No Data Transfer PH,PL MR * src stringMULAPLS, MULSPL, MULSPLS, MULTPL, Multpls Mulapl Multiply and Accumulate ResultPH ,PL MR * src Background. See .8 for more detailMR * src Mulapls Multiply String and Accumulate ResultMULAPL, MULSPL, MULSPLS, MULTPL, Multpls Syntax Description Mulspl adrs Mulspl Multiply and Subtract PL From AccumulatorOccuring in the background. See .8 for more details MULSPLS, MULTPL, MULTPLS, MULAPL, MulaplsSyntax Description Mulspls adrs Mulspls Multiply String and Subtract PL From AccumulatorFrom dest string MULSPL, MULTPL, MULTPLS, MULAPL, MulaplsMultpl Multiply and Transfer PL to Accumulator MULTPL, MULAPL, MULAPLS, MULSPL, Mulspls MultplsExecution PH, PL MR * src PC PC + Flags Affected Stored in An stringExample 4.14.46.1 Negac A3~, A3, ±±A Negac Twos Complement Negation of AccumulatorAccumulator NEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, NotacsNEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs Assembly Language Instructions 141Negacs Twos Complement Negation of Accumulator String Dest accumulator stringExecution PC PC + 14.48 NOP No OperationRPT Example 4.14.49.1 Notac A3~, A3, ±±A Notac Ones Complement Negation of AccumulatorNOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, Xors NEGAC, NegacsA3~ Notacs Ones Complement Negation of Accumulator StringAccumulator string NegacsTFn bits in Stat register are set accordingly 14.51 or Bitwise Logical orAccumulator pointers are allowed with some operand types Or A0, *R0++R5 ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NotacsOr TF1, *R6+0x22 OR, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs 14.52 ORB Bitwise or ByteOr src Accumulator is affectedORS A0, A0~, A0 14.53 ORS Bitwise or StringPC + w Flags Affected OR, ORB, AND, ANDS, XOR, XORS, NOTAC, NotacsAddress is multipled by 4 to get the actual port address 14.54 OUTOUTS, IN, INS Port6 , An ~ Outs Output String to PortPort6 specified in the instruction OUT, IN, INSCALL, i.e., RET followed by a RET should not be allowed Assembly Language Instructions 15114.56 RET Return From Subroutine CALL, Ccc PC TOSSflag , Stag , Rtag Rflag Reset Memory FlagExample 4.14.57.2 Rflag *R6 + STAT.FM Reset Fractional Mode SyntaxResets the fractional mode. Clears FM bit of Stat 14.58 RFMStat .OM Rovm Reset Overflow ModeSaturation output normal mode Resets the overflow mode to zeroAfter execution completes 14.60 RPT Repeat Next InstructionLoad src to repeat counter Load imm8 to repeat counterRtag *R6+0x0003 Rtag Reset TagStag , Rflag , Sflag Rtag *R6+0x0002SXM 14.62 RXM Reset Extended Sign ModeAssembly Language Instructions 157 STAT.XMSflag Set Memory Flag Address flagadrs only accesses the 17 th bitRflag , Stag , Rtag Set fractional mode. Set FM bit of Stat to 14.64 SFM Set Fractional ModeMode for signed fractional arithmetic Assembly Language Instructions 159Shls 14.65 SHL Shift LeftPH , PL Accumulator. Use Shlac for this purposeExample 4.14.66.2 Shlac A1~, A1, ±±A Shlac Shift Left AccumulatorIts offset. LSB of result is set to zero Shift accumulator A1 by one bit to the leftAccumulators in the string Shlacs Shift Left Accumulator String IndividuallyExample 4.14.68.3 Shlapl A1, A1, ++A Shlapl Shift Left with AccumulateExample 4.14.68.1 Shlapl A0, *R4++R5 Shlapl A2, *R1++Shift data memory string left, add PL to a n Shlapls Shift Left String With AccumulateShift a n ~ string left, addb PL to a n ~ An~ Assembly Language Instructions 165Shls Shift Left Accumulator String to Product Execution PH, PLExample 4.14.71.3 Shlspl A1, A1, ++A Shlspl Shift Left With Subtract PLExample 4.14.71.1 Shlspl A0, *R4++R5 Shlspl A2, *R1++Syntax Description Shlspls An, adrs Shlspls Shift Left String With Subtract PLBit to the next accumulator Shlspl , Shltpl , SHLTPLS, SHLAPL, ShlaplsExample 4.14.73.3 Shltpl A1, A1, ++A Shltpl Shift Left and Transfer PL to AccumulatorExample 4.14.73.1 Shltpl A0, *R4++R5 Shltpl A2, *R1++SHLTPL, SHLAPL, SHLAPLS, SHLSPL, Shlspls Shltpls Shift Left String and Transfer PL to AccumulatorExecution PH, PL src SV Receives the same data as PHExample 4.14.75.2 Shrac A1~, A1, ++A Shrac Shift Accumulator RightRegister Shift right one bit the accumulator A1Shltpls Assembly Language Instructions 171Shracs Shift Accumulator String Right SHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, ShltplSTAT.OM Set Overflow Mode SyntaxOutput DSP mode SovmRTAG, RFLAG, Sflag StagStag *0x401 An ~ , An ~ , imm16 , next a 14.79 SUB SubtractDest, src , src1 , next a An ~ , An , adrs , next aSUB R3, R5 Example 4.14.79.2 SUB A0, A0, 2, ++ASUB A1, A1~, A1 SUB A3~, A3, *R4ÐSyntax Description Subb a n, imm8 Subb Subtract ByteSubtract 0x45 from accumulator A2 byte Subtract 0xF2 from register R3 byteSubs Subtract Accumulataor String Assembly Language Instructions 177Subs A2, A2~, A2 Subs A2, A2, A2~Subs A3~, A3~, PH RXM 14.82 SXM Set Extended Sign ModeSets extended sign mode status register Stat bit 0 to Assembly Language Instructions 179See Also RET, IRET, CALL, C cc Example Vcall Vectored CallPush PC + 0x7F00 R7 R7 + Flags AffectedTAG bit is set accordingly Src is flagadrs 14.84 XOR Logical XORXOR src For two operands XOR src For three operandsExample 4.14.84.1 XOR A1, A1, 0x13FF XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NotacsExample 4.14.84.2 XOR A0, A0, 2, ++A Xorb Logical XOR Byte Assembly Language Instructions 183XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Xors A2, A2~, A2 Xors Logical XOR StringDest string XOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, NotacsZacs Reset the content of accumulator A0 to zeroAssembly Language Instructions 185 14.87 ZAC Zero AccumulatorZero the specified accumulator string Reset the content of offset accumulator string A1~ to zeroZacs Zero Accumulator String PC PC + Flags Affected ZF =Instruction Set Encoding Assembly Language Instructions 187Instruction Set Encoding 188 Assembly Language Instructions 189 190 Assembly Language Instructions 191 192 Assembly Language Instructions 193 194 True condition Not true condition Assembly Language Instructions 195Instruction Set Summary Rx, R5 Pma16 , Rmod Assembly Language Instructions 197An~, An~ , next a An~, imm16 , next aAn ~, imm16 , next a Adrs, a n~ , next a ±46~, adrs , next a ±46 Adrs , *An ±46Adrs, TOS Assembly Language Instructions 199Adrs, SV Adrs, APn~ , a n~ MR, adrs~ , next a ~, a n~ , next aAn~, An~, An An~, An~ , next a NR+3 Assembly Language Instructions 201TFn, flagadrs NR+3 TFn, cc , Rx An~, An~, pma16~, a n~, PH ~, a n~~, a n, a n~ , next a ~, a n, a n~Conditional on ZF=0 and SF=1 Not condition ZF≠0 or SF≠1 Conditional on RCF=1 Not condition RCF=0Conditional on RZF=0 and RCF=1 Not condition RZF≠0 or RCF≠1 Conditional on RZF=1 Not condition RZF=0Instruction Set Summay 204Assembly Language InstructionsMC = Pllm value+1 ⋅ 131.07 kHz 206Assembly Language Instructions Summay Instruction Set Summay 208Assembly Language Instructions Code Development Tools Introduction MSP50C6xx Software Development Tool MSP50C6xx Software Development ToolCode Development Tools Requirements RequirementsPC Requirements Development RequirementsHardware Installation Hardware InstallationSoftware Installation Software Installation±5. Setup Window ±6. Exit Setup Dialog ±8. Choose Destination Location Dialog ±9. Select Program Folder Dialog ±10. Copying Files ±11.Setup Complete Dialog Open Screen Software EmulatorSoftware Emulator ±13. Project Menu Projects ±15. File Menu Options±16. MSP50P614/MSP50C614 Code Development Windows Description of Windows±17. RAM Window ±18. CPU Window ±19. Program Window ±20. Hardware Breakpoint Dialog ±21. Inspect Dialog Debugging a Program ±23. I/O Ports Window±24. Debug Menu Software Emulator ±25. Eprom Programming Dialog ±26. Trace Mode ±27. Init Menu Option Initializing ChipEmulator Options ±28. Options Menu Emulator Online Help System ±30. Windows Menu Options±31. Context Sensitive Help System Known Differences, Incompatibilities, Restrictions Assembler DLL AssemblerAssembler Examples Assembler Directives~ indicates bitwise complement #IFDEF #ELSE see #IF and #IFDEF#ENDIF Example #IFDEF symbol#IFNDEF symbol #ELSEAssembler Linker LinkerIerr=LINKMAIN sourcefile,exefile C± ± Compiler± ± Compiler Foreword External References Variable TypesType Name Mnemonic Range Size in Bytes Example With Arguments Defines a replacement string for a given string4 C± ± Directives Without ArgumentsMust be present to terminate a #ifdef or #ifndef directive See #if directiveInclude Files String Functions Function Prototypes and DeclarationsInitializations RAM Usage±1. String Functions An example of the use of xferconst is Constant FunctionsSigned comparison of a and b. a is in A0, b is in A0~ Implementation DetailsComparisons This section is C± ± specificUnsigned comparison of a and b. a is in A0, b is in A0~ Assembly VectorLow Address High Address DivisionFunction Calls Stack frame has the following structureOn RET Programming ExampleCmmfunc bidonint i1,char *i2 is valid, but On CallIfteststringm2,0,lgm2,LTSN Programming Example, C ±± With Assembly Routines ±±±±±±±±±±±±±±± Addb R7,2 To C function return in cmmreturn ±±±±±±±±±±±±±± OldR5 Return Addr Param R7,R5 Stack data Param ±±±±±±±±±±±±±± To ASM function return External ProvidedData Iprtc Implementation Details Nop ret Dummy interrupt routines Implementation Details Implementation Details Reported Bugs With Code Development Tool Beware of Stack CorruptionBeware of Stack Corruption Page Applications Application Circuits Application CircuitsMSP50P614 only 100 kΩ MSP50C614/MSP50P614 Initialization Codes MSP50C614/MSP50P614 Initialization CodesFile init.asm Begloop ~,TIM2REFOSC + TIM2IMR Texas Instruments C614 Synthesis Code Texas Instruments C614 Synthesis CodeOverview Getting StartedDirectory Structure Running the ProgramSpkram.irx ROM File DescriptionModifying Files and Projects RAM UsageAdding Another Module Understanding the RAM MapCreating a New Project Memory OverlayThese files may be edited for special purpose code These files should never be editedROM Usage With Respect to Various Synthesis Algorithms ROM Usage With Respect to Various Synthesis AlgorithmsCustomer Information Die Bond-Out Coordinates Mechanical InformationMechanical Information Customer Information Package Information±1 -Pin PJM Mechanical Information ±2 -Pin Grid Array Package for the Development Device, P614 ±3 Pin Grid Array PGA Package Leads, P614 Customer Information Fields in the ROM Customer Information Fields in the ROMDevice Production Sequence Speech Development CycleSpeech Development Cycle Nprf Device Production Sequence614 Ordering InformationNew Product Release Forms Ordering InformationNew Product Release Forms Authorization to Generate MASKS, PROTOTYPES, and Risk UnitsPage MSP50C605 Preliminary Data Introduction Features ArchitectureArchitecture FeaturesPort Name IO Location MSP50C614 MSP50C605 Port Description Function Name Address 3 I/O Pins1 RAM 2 ROMFigure A±1. MSP50C605 Architecture Peripheral Ports Program MemoryData Memory Data ROMPlastic Package Description Pin# Page MSP50C604 Preliminary Data Introduction Features Architecture PackagingIntroduction MSP50C604 Preliminary Data ArchitectureFigure B±1. MSP50C604 Block Diagram Host Write Sequence Slave Mode OperationHost Read Sequence Data Memory Program MemoryPeripheral Ports Interrupts Packaging PackagingPlastic Package Packaging Topic MSP50C605 Data SheetMSP50C605 Data Sheet