Texas Instruments MSP50C614 manual Branch on D Port, Internal and External Interrupts

I/O

3.1.4Branch on D Port

Instructions exist to branch conditionally depending upon the state of ports D0 and D1. These conditionals are COND1 and COND2, respectively. The condi- tionals are supported whether the D0 and D1 ports are configured as inputs or as outputs. The following table lists the four possible logical states for D0 and D1, along with the software instructions affected by them.

	D0 = 1	COND1 = TRUE. . .	CIN1	has its conditional call taken.
			CNIN1	has its conditional call ignored.
			JIN1	has its conditional jump taken.
			JNIN1	has its conditional jump ignored.
	D0 = 0	COND1 = FALSE. . .	CIN1	has its conditional call ignored.
			CNIN1	has its conditional call taken.
			JIN1	has its conditional jump ignored.
			JNIN1	has its conditional jump taken.
²	D1 = 1	COND2 = TRUE. . .	CIN2	has its conditional call taken.
			CNIN2	has its conditional call ignored.
			JIN2	has its conditional jump taken.
			JNIN2	has its conditional jump ignored.
²	D1 = 0	COND2 = FALSE. . .	CIN2	has its conditional call ignored.
			CNIN2	has its conditional call taken.
			JIN2	has its conditional jump ignored.
			JNIN2	has its conditional jump taken.

²COND2 may be associated instead with the comparator function, if the comparator Enable bit is set. Please refer to Section 3.3, Comparator, for details.

3.1.5Internal and External Interrupts

INT3, INT4, INT6, and INT7 are external interrupts which may be triggered by events on the PD2, PD3, PD4, and PD5 pins. These interrupts are supported whether the D-port pins are programmed as inputs or outputs. (When programmed as an output, the pin effectively triggers a software interrupt.)

INT5 is an external interrupt triggered by a falling-edge event on any of the F-port inputs. It is triggered if all eight port-F pins are held high, and then one or more of these pins is taken low.

Only the transition from 0xFFh (all high) to (one or more pins) low will trigger the INT5 event. If any F-port pin is continuously held low and another is toggled high-to-low, no interrupt is detected at the toggling pin. After all F-port pins have been brought high again, then it is possible for a new INT5 trigger to occur.

INT0 is an internal interrupt (highest priority) which is triggered by an underflow condition on the DAC Timer (see Section 3.2.2, DAC Control and Data

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