MSP50C614 Mixed-Signal Processor Users Guide
Important Notice
How to Use This Manual
About This Manual
Notational Conventions
This document uses the following conventions
This provides three choices *, *+, or *±
Csr ±a /user/ti/simuboard/utilities
Notational Conventions
Information About Cautions and Warnings
Trademarks
This book may contain cautions and warnings
Information About Cautions and Warnings
Page
Contents
Assembly Language Instructions
Contents
Contentsix
Code Development Tools
Applications
ROM Usage With Respect to Various Synthesis Algorithms
Customer Information
Contentsxi
Figures
±10
±11
±12
±13
Tables
±32
±33
±34
±35
Page
Introduction to the MSP50C614
Features of the C614
Features of the C614
Applications
Applications
Introduction to the MSP50C614
Development Device MSP50P614
Development Device MSP50P614
Functional Description
Functional Description
C605 and C604 Preliminary Information
C605 and C604 Preliminary Information
±1. Functional Block Diagram for the C614
Crystal Oscillator Operation Connections
Resistor Trim Operation Connections
±3. Reset Circuit
±1. Signal and Pad Descriptions for the C614
Terminal Assignments and Signal Descriptions
Terminal Assignments and Signal Descriptions
±2. MSP50C614 100-Pin PJM Plastic Package Pinout Description
Description Pin #
PD0 PD1 PD2 PD3 PD4 PD5 PD6
±5 Pin Grid Array Package for the Development Device, P614
VPP VSS VDD DAC M DAC P
MSP50C614 Architecture
Architecture Overview
±1. MSP50C614 Core Processor Block Diagram
MSP50C614 Architecture
ALU
Computation Unit
Multiplier
±1. Signed and Unsigned Integer Representation
Computation Unit
Computation Unit
±3. Overview of the Multiplier Unit Operation
Arithmetic Logic Unit
Accumulator Block
±4. Overview of the Arithmetic Logic Unit
Accumulator Block
AC0 . . . AC31
Accumulator Block Pointers
AP0 . . . AP3
Data Memory Address Unit
Data Memory Address Unit
RAM Configuration
±6. Data Memory Address Unit
Data Memory Addressing Modes
Bit Logic Unit
Program Counter Unit
Program Counter Unit
Memory Map
Memory Organization RAM and ROM
Memory Organization RAM and ROM
±7. C614 Memory Map not drawn to scale
Peripheral Communications Ports
Reset LOW
±2. Summary of C614s Peripheral Communications Ports
Interrupt Vectors
Interrupt Name ROM address Event Source Interrupt Priority
ROM Code Security
Block Protection Word
Write only
= the value programmed at TM5… TM0 true
Protection marker
≡ the binary complement of NTM
= the value programmed at FM5… FM0 false
Macro Call Vectors
Interrupt Logic
Interrupt Logic
IFR
Interrupt Logic
±8. Interrupt Initialization Sequence
Timer Registers
Timer Registers
Triggers INT1 on underflow
Timer Registers
Clock Control
Oscillator Options
PLL Performance
Clock Control
±9. PLL Performance
Clock Speed Control Register
CPU
ClkSpdCtrl register
Rtrim Register Read Only Applies to MSP50C614 Device Only
RTO Oscillator Trim Adjustment
ClkSpdCtrl Value Copied Shaded
Execution Timing
Execution Timing
Reduced Power Modes
Reduced Power Modes
Reduced Power Modes
Reduced Power Modes
±3. Programmable Bits Needed to Control Reduced Power Modes
Light MID Deep
Component Determined
→ deeper sleep … relatively less power →
By Controls
Deeper sleep … Relatively less power → Event Determined
Global interrupt enable is SET
Peripheral Functions
General-Purpose I/O Ports
I/O
Port a Port B Port C Port D Port E
Peripheral Functions
Dedicated Input Port F
Input Port F
Dedicated Output Port G
Totem-Pole Output Port G
Branch on D Port
Internal and External Interrupts
±1. Interrupts
Interrupt Vector Source Trigger Event Priority Comment
Digital-to-Analog Converter DAC
Pulse-Density Modulation Rate
DAC Control and Data Registers
Digital-to-Analog Converter DAC
Overflow bits Least-significant data value Ignored bits
PDM Clock Divider
±1. PDM Clock Divider
Digital-to-Analog Converter DAC
CPU
Pllm
Comparator
For INT7 is enabled
TIMER1 starts counting
Cleared. Refer to .7, Interrupt Logic, for more details
Address
Comparator
Interrupt/General Control Register
Interrupt/General Control Register
IntGenCtrl register
Interrupt/General Control Register
Hardware Initialization States
Hardware Initialization States
Hardware Initialization States
Bit Bit Name Initialized Value Description
RZF
Page
Assembly Language Instructions
Introduction
System Registers
Top of Stack, TOS
Assembly Language Instructions
System Registers
Product Low Register PL
Product High Register PH
Accumulators AC0±AC31
Indirect Register R0±R7
Accumulator Pointers AP0±AP3
Bit
String Register STR
Status Register Stat
±1. Status Register Stat
Function
Instruction Syntax and Addressing Modes
1 MSP50P614/MSP50C614 Instruction Syntax
±2. Addressing Mode Encoding
Addressing Modes
Opcode
Next a
±4. Addressing Mode Bits and adrs Field Description
±3. Rx Bit Description
±5. MSP50P614/MSP50C614 Addressing Modes Summary
±6. Auto Increment and Auto Decrement Modes
Flag addressing mode encoding, flagadrs
Flag Repeat
Flagadrs
Clocks Words Addressing Operation, ² Syntax
Syntax
Immediate Addressing
Example
MOV *0x012F * 2, *A0
Direct Addressing
Mulr *0x02A1
±9. Indirect Addressing Syntax
Indirect Addressing
SyntaxOperation
Relative Addressing
MOV A2, *R0
*R4++
Movb *R7++, A3
A0, *R3+R5
Short Relative
MOV A3, *R6+0x10
Long Relative
Flag Addressing
TF1, *0x20
Or TF2, *R6+0x02
XOR TF1, *R6+0x20
8 Tag/Flag Bits
Possible sources of confusion Consider the following code
TF1,*ram1 TF1 bit in Stat is set!?
±10. Symbols and Explanation
Symbol Explanation
Instruction Classification
Instruction Classification
±11. Instruction Classification
±11. Symbols and Explanation
Class Sub- Description
Class Sub Description
±12. Classes and Opcode Definition
Class 1 Instructions Memory and Accumulator Reference
±13. Class 1 Instruction Encoding
±14. Class 1a Instruction Description
C1a ~A~
C1b
±15. Class 1b Instruction Description
C1b Mnemonic Description
Class 2 Instructions Accumulator and Constant Reference
Shltpls a n, adrs
±17. Class 2a Instruction Description
±16. Class 2 Instruction Encoding
C2a Mnemonic Description
±18. Class 2b Instruction Description
Class 3 Instruction Accumulator Reference
C2b Mnemonic Description
ADD An ~, An ~, imm16 , next a
±20. Class 3 Instruction Description
±19. Class 3 Instruction Encoding
Mnemonic Description
Zero or be set equal to the sign bit Xsgm dependent
MOV SV, An~ , next a
Class 4 Instructions Address Register and Memory Reference
±21. Class 4a Instruction Encoding
±22. Class 4a Instruction Description
±23. Class 4b Instruction Description
±24. Class 4c Instruction Description
±25. Class 4d Instruction Description
±26. Class 5 Instruction Encoding
Class 5 Instructions Memory Reference
±27. Class 5 Instruction Description
RET²
Class 6 Instructions Port and Memory Reference
±28. Class 6a Instruction Encoding
±29. Class 6a Instruction Description
C6a Mnemonic Description
Class 7 Instructions Program Control
±30. Class 6b Instruction Description
C6b Mnemonic Description
±31. Class 7 Instruction Encoding and Description
Vector8
Jcc
Ccc
Class 8 Instructions Logic and Bit
±32. Class 8a Instruction Encoding
±33. Class 8a Instruction Description
±34. Class 8b Instruction Description
Class 9 Instructions Miscellaneous
C8a Mnemonic Description
±35. Class 9a Instruction Encoding
±36. Class 9a Instruction Description
±37. Class 9b Instruction Description
C9a Mnemonic Description
Bit, Byte, Word and String Addressing
±38. Class 9c Instruction Description
±39. Class 9d Instruction Description
C9c Mnemonic Description
±3. Data Memory Organization and Addressing
Mode Address Used Data Order Rx Post modify ²
±40. Data Memory Address and Data Relationship
Movb A0, *0x0003
MOV A0, *0x0004
±4. Data Memory Example
Which uses the absolute word memory address
Rflag
MSP50P614/MSP50C614 Computational Modes
MSP50P614/MSP50C614 Computational Modes
Computational Setting Resetting Function Mode Instruction
±41. MSP50P614/MSP50C614 Computational Modes
SXM
Example 4.6.2 Sovm
Example 4.6.1 Sovm
Example 4.6.1 SXM
Hardware Loop Instructions
Hardware Loop Instructions
±42. Hardware Loops in MSP50P614/MSP50C614
Syntax Operation Limitations
String Instructions
±43. Initial Processor State for String Instructions
String Instructions
Registers register# = value
Mulapl A0, A0~
Lookup Instructions
±44. Lookup Instructions
Lookup Instructions
Instructions Description Data Transfer
MOV An, adrs SUB An MOV An, *An
Input/Output Instructions
Special Filter Instructions
Input/Output Instructions
Xk±2 Xk+2 Xk±1 xk+1 32 or Yk = Σm =0..N hm⋅xk-m
Special Filter Instructions
STR,N±2
STR,0
0x0104
After FIR/COR execution
Important note about setting the Stat register
Firkcoeffs
Coeffarray address FIRK/CORK only Program memory FIRK/CORK
Coeffarray Samplebuf address
FIR/COR only = 0..N
Coeffarray
Samplebuf Coeffarray is stored
Conditionals
Conditionals
Symbol Meaning
Operands
≤ dma6 ≤ ≤ dma16 ≤
≤ port4 ≤ ≤ port6 ≤
Adrsn
Clk
Dma n
Flg
Pma n
Offset n
Port n
±45. Auto Increment and Decrement
±46. Addressing Mode Bits and adrs Field Description
±47. Flag Addressing Syntax and BIts
Individual Instruction Descriptions
Individual Instruction Descriptions
14.1 ADD Add word
Execution
Description
See Also
PC PC + Flags Affected
Addb
Opcode
Adds Add String
Clock , clk Words , w
Adds A1, A1~, A1
14.4 Bitwise
A3, *R4б
ANDS, ANDB, OR, ORB, ORS, XOR, XORB, Xors
TF2, *0x0020
Andb Bitwise and Byte
Src byte PC PC +
OF, SF, ZF, CF are set accordingly
Clock , clk Word , w
Ands Bitwise and String
Ands A0, A0~, A0
Ands A0, A0~, *R2
Clock, clk Word, w
Begloop Begin Loop
Save next instruction address PC +
Flags Affected None Opcode
Order to loop N times
Call Unconditional Subroutine Call
TOS
TOS PC +
R7 +
NOP
±48. Names for cc
True condition Not true condition
Syntax Alternate Syntax Description
CALL, VCALL, RET, Iret
0x2010
CTF1
Crnbe
14.10 CMP Compare Two Words
Stat flags set by src ± src1 operation
PC = PC + w
CMPB, CMPS, Jcc, Ccc
CMP R2, 0xfe20
CMP R0, R5
Cmpb Compare Two Bytes
Cmpb R3
Cmps Compare Two Strings
PC PC + w Flags Affected
Cmps A1~
Cmps A2, A2~
14.13 COR Correlation Filter Function
3n R+2
Xeven = R xeven + R5
Xeven ++
Cork Correlation Filter Function
Sample data. During Cork execution, interrupt is queued
An, *Rx 3nR+2
Rxeven = Rxeven + R5
Endloop End Loop
Decrement R4 by n 1 or First address after Begloop Else
Argument, it assumes n =1
BEGLOOP, Inte
Extsgn Sign Extend Word
An~ , next a
Copy accumulator sign flag SF to all 16 bits of An~
Dest , mod
Extsgns Sign Extend String
Extsgn
14.18 FIR FIR Filter Function Coefficients in RAM
2n R+2
Assembly Language Instructions 101
Be even. During Firk execution, interrupts are queued
Firk
RPT, FIR, COR, Cork
Idle Halt Processor
Assembly Language Instructions 103
Stop processor clocks
INS, OUT, Outs
14.21 Input From Port Into Word
A2~, 0x3d
14.22 INS Input From Port Into String
IN, OUT, Outs
Intd Interrupt Disable
IM is Stat bit
Stat to
INTE, Iret
Assembly Language Instructions 107
Inte Interrupt Enable
INTD, Iret
Iret Return From Interrupt
R7 R7 ±
See Also RET, CALL, C cc, INTE, Intd Description
Return from interrupt. Pop top of stack to program counter
14.26 Jcc Conditional Jumps
PC PC +
110
If test condition is false, a NOP is executed
See Also JMP, CALL, C cc Example
JNZ
JE 0x2010, R3++R5
JIN1 0x2010, R1±±
14.27 JMP Unconditional Jump
Post±modify Rx if specified
RCF and RZF affected by post±modification of Rx
See Also Jcc, CALL, Ccc Example
14.28 MOV Move Data Word From Source to Destination
XSF, XZF are set accordingly
Clock, clk Word, w With RPT, clk Class
TFn, cc , Rx
STR, imm8
116
With some operand types
MOVU, MOVT, MOVB, MOVBS, Movs
Example 4.14.28.10 MOV MR, A3, ±±A
Example 4.14.28.11 MOV A1~, *A1
Example 4.14.28.12 MOV *0x0200 * 2, R0
Example 4.14.28.13 MOV R1, 0x0200
Example 4.14.28.15 MOV *0x0200 * 2, R0
Transfer R5 to R0 Example
Example 4.14.28.18 MOV *R6 + 8 * 2, DP
Execution + PH
Movaph Move With Adding PH
MOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs
Movaphs Move With Adding PH
Execution An + PH
Background. See .8 for more details
MOVAPH, MOVTPH, MOVTPHS, MOVSPH, Movsphs
Movb Move Byte From Source to Destination
Copy value of unsigned src byte to dest byte
Movb A0, *R2
Copy data memory byte pointed by R2 to accumulator A0
Movb A0, 0xf2
Movb *R2, A0
Movb R2
Movbs Move Byte String from Source to Destination
TAG bit is set to bit 17 th value
Movbs A2, *0x0200
Movbs *0x0200, A2
Movs Move String from Source to Destination
Movs A1, A1~
Movs A2~
Movs A1~, A1
Movsph
Assembly Language Instructions 127
MOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs
Second word ± PH MR contents of adrs
Movsphs Move String With Subtract From PH
Details
MOVSPH, MOVAPH, MOVAPHS, MOVTPH, Movtphs
Movt
PC PC + w Flags Affected None Opcode
Available
MOVU, MOV, MOVT, MOVB, MOVBS, Movs
Movu Move Data Unsigned
TAG bit is set accordingly UM is set to
MOV, MOVB, MOVT, MOVBS, Movs
Copy the value pointed by R3 to MR
Assembly Language Instructions 131
14.38 MUL Multiply Rounded
MR * src PC PC + w Flags Affected
Accumulator pointer if specified
MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, Mulapl
Length nS+2, where nS is the value in STR register
Muls Multiply String With No Data Transfer
PH,PL MR * src string
MUL, MULR, MULAPL, MULSPL, MULSPLS, MULTPL, Multpls
Mulapl Multiply and Accumulate Result
PH ,PL MR * src
Background. See .8 for more detail
MULAPLS, MULSPL, MULSPLS, MULTPL, Multpls
MR * src
Mulapls Multiply String and Accumulate Result
MULAPL, MULSPL, MULSPLS, MULTPL, Multpls
Mulspl Multiply and Subtract PL From Accumulator
Occuring in the background. See .8 for more details
MULSPLS, MULTPL, MULTPLS, MULAPL, Mulapls
Syntax Description Mulspl adrs
Mulspls Multiply String and Subtract PL From Accumulator
From dest string
MULSPL, MULTPL, MULTPLS, MULAPL, Mulapls
Syntax Description Mulspls adrs
Multpl Multiply and Transfer PL to Accumulator
Multpls
Execution PH, PL MR * src PC PC + Flags Affected
Stored in An string
MULTPL, MULAPL, MULAPLS, MULSPL, Mulspls
Negac Twos Complement Negation of Accumulator
Accumulator
NEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs
Example 4.14.46.1 Negac A3~, A3, ±±A
Assembly Language Instructions 141
Negacs Twos Complement Negation of Accumulator String
Dest accumulator string
NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs
Execution PC PC +
14.48 NOP No Operation
RPT
Notac Ones Complement Negation of Accumulator
NOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, Xors
NEGAC, Negacs
Example 4.14.49.1 Notac A3~, A3, ±±A
Notacs Ones Complement Negation of Accumulator String
Accumulator string
Negacs
A3~
TFn bits in Stat register are set accordingly
14.51 or Bitwise Logical or
Accumulator pointers are allowed with some operand types
Or A0, *R0++R5
ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs
Or TF1, *R6+0x22
14.52 ORB Bitwise or Byte
Or src
Accumulator is affected
OR, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs
14.53 ORS Bitwise or String
PC + w Flags Affected
OR, ORB, AND, ANDS, XOR, XORS, NOTAC, Notacs
ORS A0, A0~, A0
Address is multipled by 4 to get the actual port address
14.54 OUT
OUTS, IN, INS
Outs Output String to Port
Port6 specified in the instruction
OUT, IN, INS
Port6 , An ~
Assembly Language Instructions 151
14.56 RET Return From Subroutine CALL, Ccc
PC TOS
CALL, i.e., RET followed by a RET should not be allowed
Sflag , Stag , Rtag
Rflag Reset Memory Flag
Example 4.14.57.2 Rflag *R6 +
Reset Fractional Mode Syntax
Resets the fractional mode. Clears FM bit of Stat
14.58 RFM
STAT.FM
Rovm Reset Overflow Mode
Saturation output normal mode
Resets the overflow mode to zero
Stat .OM
14.60 RPT Repeat Next Instruction
Load src to repeat counter
Load imm8 to repeat counter
After execution completes
Rtag Reset Tag
Stag , Rflag , Sflag
Rtag *R6+0x0002
Rtag *R6+0x0003
14.62 RXM Reset Extended Sign Mode
Assembly Language Instructions 157
STAT.XM
SXM
Sflag Set Memory Flag
Address flagadrs only accesses the 17 th bit
Rflag , Stag , Rtag
14.64 SFM Set Fractional Mode
Mode for signed fractional arithmetic
Assembly Language Instructions 159
Set fractional mode. Set FM bit of Stat to
14.65 SHL Shift Left
PH , PL
Accumulator. Use Shlac for this purpose
Shls
Shlac Shift Left Accumulator
Its offset. LSB of result is set to zero
Shift accumulator A1 by one bit to the left
Example 4.14.66.2 Shlac A1~, A1, ±±A
Shlacs Shift Left Accumulator String Individually
Accumulators in the string
Shlapl Shift Left with Accumulate
Example 4.14.68.1 Shlapl A0, *R4++R5
Shlapl A2, *R1++
Example 4.14.68.3 Shlapl A1, A1, ++A
Shift data memory string left, add PL to a n
Shlapls Shift Left String With Accumulate
Shift a n ~ string left, addb PL to a n ~
Assembly Language Instructions 165
Shls Shift Left Accumulator String to Product
Execution PH, PL
An~
Shlspl Shift Left With Subtract PL
Example 4.14.71.1 Shlspl A0, *R4++R5
Shlspl A2, *R1++
Example 4.14.71.3 Shlspl A1, A1, ++A
Shlspls Shift Left String With Subtract PL
Bit to the next accumulator
Shlspl , Shltpl , SHLTPLS, SHLAPL, Shlapls
Syntax Description Shlspls An, adrs
Shltpl Shift Left and Transfer PL to Accumulator
Example 4.14.73.1 Shltpl A0, *R4++R5
Shltpl A2, *R1++
Example 4.14.73.3 Shltpl A1, A1, ++A
Shltpls Shift Left String and Transfer PL to Accumulator
Execution PH, PL src SV
Receives the same data as PH
SHLTPL, SHLAPL, SHLAPLS, SHLSPL, Shlspls
Shrac Shift Accumulator Right
Register
Shift right one bit the accumulator A1
Example 4.14.75.2 Shrac A1~, A1, ++A
Assembly Language Instructions 171
Shracs Shift Accumulator String Right
SHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, Shltpl
Shltpls
Set Overflow Mode Syntax
Output DSP mode
Sovm
STAT.OM
RTAG, RFLAG, Sflag
Stag
Stag *0x401
14.79 SUB Subtract
Dest, src , src1 , next a
An ~ , An , adrs , next a
An ~ , An ~ , imm16 , next a
Example 4.14.79.2 SUB A0, A0, 2, ++A
SUB A1, A1~, A1
SUB A3~, A3, *R4Ð
SUB R3, R5
Subb Subtract Byte
Subtract 0x45 from accumulator A2 byte
Subtract 0xF2 from register R3 byte
Syntax Description Subb a n, imm8
Assembly Language Instructions 177
Subs Subtract Accumulataor String
Subs A2, A2~, A2
Subs A2, A2, A2~
Subs A3~, A3~, PH
14.82 SXM Set Extended Sign Mode
Sets extended sign mode status register Stat bit 0 to
Assembly Language Instructions 179
RXM
Vcall Vectored Call
Push PC + 0x7F00
R7 R7 + Flags Affected
See Also RET, IRET, CALL, C cc Example
14.84 XOR Logical XOR
XOR src For two operands
XOR src For three operands
TAG bit is set accordingly Src is flagadrs
Example 4.14.84.1 XOR A1, A1, 0x13FF
XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs
Example 4.14.84.2 XOR A0, A0, 2, ++A
Xorb Logical XOR Byte
Assembly Language Instructions 183
XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs
Xors Logical XOR String
Dest string
XOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs
Xors A2, A2~, A2
Reset the content of accumulator A0 to zero
Assembly Language Instructions 185
14.87 ZAC Zero Accumulator
Zacs
Reset the content of offset accumulator string A1~ to zero
Zacs Zero Accumulator String
PC PC + Flags Affected ZF =
Zero the specified accumulator string
Instruction Set Encoding
Assembly Language Instructions 187
Instruction Set Encoding
188
Assembly Language Instructions 189
190
Assembly Language Instructions 191
192
Assembly Language Instructions 193
194
Assembly Language Instructions 195
True condition Not true condition
Instruction Set Summary
Pma16 , Rmod Assembly Language Instructions 197
An~, An~ , next a
An~, imm16 , next a
Rx, R5
Adrs, a n~ , next a ±46
~, adrs , next a ±46
Adrs , *An ±46
An ~, imm16 , next a
Assembly Language Instructions 199
Adrs, SV
Adrs, APn
Adrs, TOS
MR, adrs
~ , next a
~, a n~ , next a
~ , a n~
An~, An~ , next a NR+3 Assembly Language Instructions 201
TFn, flagadrs NR+3 TFn, cc , Rx
An~, An~, pma16
An~, An~, An
~, a n~
~, a n, a n~ , next a
~, a n, a n~
~, a n~, PH
Conditional on RCF=1 Not condition RCF=0
Conditional on RZF=0 and RCF=1 Not condition RZF≠0 or RCF≠1
Conditional on RZF=1 Not condition RZF=0
Conditional on ZF=0 and SF=1 Not condition ZF≠0 or SF≠1
204Assembly Language Instructions
Instruction Set Summay
MC = Pllm value+1 ⋅ 131.07 kHz
206Assembly Language Instructions
Summay
Instruction Set Summay 208Assembly Language Instructions
Code Development Tools
Introduction
MSP50C6xx Software Development Tool
MSP50C6xx Software Development Tool
Code Development Tools
Requirements
PC Requirements
Development Requirements
Requirements
Hardware Installation
Hardware Installation
Software Installation
Software Installation
±5. Setup Window
±6. Exit Setup Dialog
±8. Choose Destination Location Dialog
±9. Select Program Folder Dialog
±10. Copying Files
±11.Setup Complete Dialog
Open Screen
Software Emulator
Software Emulator
±13. Project Menu
±15. File Menu Options
Projects
Description of Windows
±16. MSP50P614/MSP50C614 Code Development Windows
±17. RAM Window
±18. CPU Window
±19. Program Window
±20. Hardware Breakpoint Dialog
±21. Inspect Dialog
±23. I/O Ports Window
Debugging a Program
±24. Debug Menu
Software Emulator
±25. Eprom Programming Dialog
±26. Trace Mode
Initializing Chip
±27. Init Menu Option
Emulator Options
±28. Options Menu
±30. Windows Menu Options
Emulator Online Help System
±31. Context Sensitive Help System
Known Differences, Incompatibilities, Restrictions
Assembler DLL
Assembler
Assembler
Examples
Assembler Directives
~ indicates bitwise complement
#ELSE see #IF and #IFDEF
#IFDEF
Example #IFDEF symbol
#IFNDEF symbol
#ELSE
#ENDIF
Assembler
Linker
Linker
Ierr=LINKMAIN sourcefile,exefile
C± ± Compiler
± ± Compiler
Foreword
External References
Variable Types
Type Name Mnemonic Range Size in Bytes Example
Defines a replacement string for a given string
4 C± ± Directives
Without Arguments
With Arguments
See #if directive
Must be present to terminate a #ifdef or #ifndef directive
Include Files
Function Prototypes and Declarations
Initializations
RAM Usage
String Functions
±1. String Functions
Constant Functions
An example of the use of xferconst is
Implementation Details
Comparisons
This section is C± ± specific
Signed comparison of a and b. a is in A0, b is in A0~
Assembly Vector
Unsigned comparison of a and b. a is in A0, b is in A0~
Division
Function Calls
Stack frame has the following structure
Low Address High Address
Programming Example
Cmmfunc bidonint i1,char *i2 is valid, but
On Call
On RET
Ifteststringm2,0,lgm2,LTSN
Programming Example, C ±± With Assembly Routines
±±±±±±±±±±±±±±±
Addb R7,2
To C function return in cmmreturn
±±±±±±±±±±±±±± OldR5 Return Addr Param R7,R5 Stack data
Param ±±±±±±±±±±±±±±
To ASM function return
Provided
External
Data
Iprtc
Implementation Details
Nop ret Dummy interrupt routines
Implementation Details
Implementation Details
Reported Bugs With Code Development Tool
Beware of Stack Corruption
Beware of Stack Corruption
Page
Applications
Application Circuits
Application Circuits
MSP50P614 only 100 kΩ
MSP50C614/MSP50P614 Initialization Codes
MSP50C614/MSP50P614 Initialization Codes
File init.asm
Begloop
~,TIM2REFOSC + TIM2IMR
Texas Instruments C614 Synthesis Code
Overview
Getting Started
Texas Instruments C614 Synthesis Code
Running the Program
Directory Structure
Spkram.irx
File Description
ROM
RAM Usage
Adding Another Module
Understanding the RAM Map
Modifying Files and Projects
Memory Overlay
These files may be edited for special purpose code
These files should never be edited
Creating a New Project
ROM Usage With Respect to Various Synthesis Algorithms
ROM Usage With Respect to Various Synthesis Algorithms
Customer Information
Die Bond-Out Coordinates
Mechanical Information
Mechanical Information
Package Information
Customer Information
±1 -Pin PJM Mechanical Information
±2 -Pin Grid Array Package for the Development Device, P614
±3 Pin Grid Array PGA Package Leads, P614
Customer Information Fields in the ROM
Customer Information Fields in the ROM
Device Production Sequence
Speech Development Cycle
Speech Development Cycle
Device Production Sequence
Nprf
Ordering Information
New Product Release Forms
Ordering Information
614
Authorization to Generate MASKS, PROTOTYPES, and Risk Units
New Product Release Forms
Page
Introduction Features Architecture
MSP50C605 Preliminary Data
Architecture
Features
Port Name IO Location MSP50C614 MSP50C605
3 I/O Pins
1 RAM
2 ROM
Port Description Function Name Address
Figure A±1. MSP50C605 Architecture
Program Memory
Data Memory
Data ROM
Peripheral Ports
Plastic Package
Description Pin#
Page
Introduction Features Architecture Packaging
MSP50C604 Preliminary Data
Introduction
MSP50C604 Preliminary Data
Figure B±1. MSP50C604 Block Diagram
Host Write Sequence
Slave Mode Operation
Host Read Sequence
Data Memory
Program Memory
Peripheral Ports
Interrupts
Packaging
Packaging
Plastic Package
Packaging
MSP50C605 Data Sheet
Topic
MSP50C605 Data Sheet
