MC = Pllm value+1 ⋅ 131.07 kHz | Texas Instruments MSP50C614

Assembly Language Instructions 4-205

MSP50C614 (MSP50P614) IO Port Description

Address

Bits

Name

R/W

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

After RESET

0x34

4

DAC Control

R/W

DM

E

P1

P0

0x0

DM

Drive Mode

E

Function

P1

P0

DAC bits

0

3x Style DAC

0

Disable DAC

0

0

8 bit

1

5x Style DAC

1

Enable DAC

1

1

9 bits

0

10 bits

0x38

16

Interrupt

R/W

CE

AR

PD

EP

E2

E1

S2

S1

D5

D4

PF

D3

D2

T2

T1

DA

0x0000

General

EP

F port Pull up

Timer Function

Interrupt enable bits: 1=enable,0=disable

Control

AR

Arm bit

CE

Comparator

S1

Timer1 source

DA

DAC Timer interrupt

S2

Timer2 source

T1

Timer 1 interrupt

T2

Timer 2 interrupt

0=disable

0 = MC

D2

PD2 rising edge interrupt

D3

PD3 falling edge interrupt

1=enable

1 = MC

PF

F port falling edge interrupt

PD

PDM clock

E1

Timer1 enable

D4

PD4 rising edge interrupt

D5

PD5 falling edge interrupt

0

MC

E2

Timer2 enable

1

MC

0 = disable

1 = enable

0x39

8

Interrupt

R/W

D5

D4

PF

D3

D2

T2

T1

DA

left

Flag

unchanged

D5

PD5 falling edge interrupt flag

DA

DAC Timer interrupt flag

Register

D4

PD4 rising edge interrupt flag

T1

Timer 1 interrupt flag

D3

PD3 falling edge interrupt flag

T2

Timer 2 interrupt flag

PF

F port falling edge interrupt flag

D2

PD2 rising edge interrupt flag

0x3A

16

Timer 1 period

R/W

T

I

M

E

R

1

P

E

R

I

O

D

0x0000

0x3B

16

Timer 1 preset

R/W

T

I

M

E

R

1

P

R

E

S

E

T

0x0000

0x3D

16

Clock

W

T4

T3

T2

T1

T0

I

C

R

M7

M6

M5

M4

M3

M2

M1

M0

0x0000

Speed

Resistor Trim bits

I

Idle bit

PLLM bits

Control

C

CRO

MC = (PLLM value+1) ⋅ 131.07 kHz

0 = disable

R

RTO

CPU clock = (PLLM value+1) ⋅ 65.536 kHz

1 = enable

0x3E

16

Timer 2 period

R/W

T

I

M

E

R

2

P

E

R

I

O

D

0x0000

0x3F

16

Timer 2 preset

R/W

T

I

M

E

R

2

P

R

E

S

E

T

0x0000

Instruction Set Summay

Image 297

Texas Instruments MSP50C614 manual MC = Pllm value+1 ⋅ 131.07 kHz

MSP50C614 specifications

The Texas Instruments MSP50C614 is a microcontroller that belongs to the MSP430 family, renowned for its low power consumption and versatile functionality. Primarily designed for embedded applications, this microcontroller is favored in various industries, including consumer electronics, industrial automation, and healthcare devices.

One of the standout features of the MSP50C614 is its ultra-low power technology, which enables it to operate in various power modes. This makes it ideal for battery-powered applications, where energy efficiency is crucial. The MSP430 architecture allows for a flexible power management system, ensuring that energy is conserved while providing robust performance.

The MSP50C614 is equipped with a 16-bit RISC CPU that delivers high performance while maintaining low power usage. With a maximum clock frequency of 16 MHz, it can execute most instructions in a single cycle, resulting in swift operation and responsive performance. This microcontroller also comes with a generous flash memory capacity, allowing developers to store large amounts of code and data conveniently.

In terms of peripherals, the MSP50C614 is highly versatile. It features a range of digital and analog input/output options, including multiple timers, GPIO ports, and various communication interfaces like UART, SPI, and I2C. This extensive set of peripherals allows for seamless integration with other components and simplifies the design of complex systems.

The integrated 12-bit Analog-to-Digital Converter (ADC) stands out as a valuable characteristic of the MSP50C614. This feature enables the microcontroller to convert physical analog signals into digital data, making it particularly useful for sensing applications and real-time monitoring.

Another noteworthy technology employed in the MSP50C614 is its support for low-voltage operations. With a broad supply voltage range, this microcontroller can function efficiently in diverse environments and is suitable for low-power applications, enhancing its practicality.

Moreover, Texas Instruments provides software support in the form of Code Composer Studio and various libraries that make it easier for developers to program and utilize the MSP50C614 effectively.

In summary, the Texas Instruments MSP50C614 microcontroller is a powerful, low-power solution equipped with the features and technologies necessary for efficient operation in a wide array of applications. Its blend of performance, flexibility, and energy efficiency makes it a popular choice among engineers and designers looking to create innovative, sustainable designs in the rapidly evolving tech landscape.

Contents

MSP50C614 Mixed-Signal Processor Users Guide Important Notice About This Manual How to Use This ManualNotational Conventions This document uses the following conventions Csr ±a /user/ti/simuboard/utilities This provides three choices *, *+, or *±Notational Conventions Trademarks Information About Cautions and WarningsThis book may contain cautions and warnings Information About Cautions and WarningsPage Contents Contents Assembly Language Instructions Code Development Tools Contentsix ROM Usage With Respect to Various Synthesis Algorithms ApplicationsCustomer Information Contentsxi Figures ±11 ±10±12 ±13 Tables ±33 ±32±34 ±35Page Introduction to the MSP50C614 Features of the C614 Features of the C614 Applications ApplicationsIntroduction to the MSP50C614 Development Device MSP50P614 Development Device MSP50P614 Functional Description Functional Description C605 and C604 Preliminary Information C605 and C604 Preliminary Information ±1. Functional Block Diagram for the C614 Resistor Trim Operation Connections Crystal Oscillator Operation Connections ±3. Reset Circuit Terminal Assignments and Signal Descriptions ±1. Signal and Pad Descriptions for the C614Terminal Assignments and Signal Descriptions Description Pin # ±2. MSP50C614 100-Pin PJM Plastic Package Pinout Description PD0 PD1 PD2 PD3 PD4 PD5 PD6 ±5 Pin Grid Array Package for the Development Device, P614 VPP VSS VDD DAC M DAC P MSP50C614 Architecture Architecture Overview MSP50C614 Architecture ±1. MSP50C614 Core Processor Block Diagram ALU Multiplier Computation Unit±1. Signed and Unsigned Integer Representation Computation Unit Computation Unit Arithmetic Logic Unit ±3. Overview of the Multiplier Unit Operation Accumulator Block ±4. Overview of the Arithmetic Logic Unit AC0 . . . AC31 Accumulator BlockAccumulator Block Pointers AP0 . . . AP3 Data Memory Address Unit Data Memory Address Unit ±6. Data Memory Address Unit RAM Configuration Data Memory Addressing Modes Program Counter Unit Bit Logic UnitProgram Counter Unit Memory Organization RAM and ROM Memory MapMemory Organization RAM and ROM Peripheral Communications Ports ±7. C614 Memory Map not drawn to scale ±2. Summary of C614s Peripheral Communications Ports Reset LOW Interrupt Name ROM address Event Source Interrupt Priority Interrupt Vectors ROM Code Security Write only Block Protection Word Protection marker = the value programmed at TM5… TM0 true≡ the binary complement of NTM = the value programmed at FM5… FM0 false Interrupt Logic Macro Call VectorsInterrupt Logic IFR Interrupt Logic ±8. Interrupt Initialization Sequence Timer Registers Timer Registers Triggers INT1 on underflow Timer Registers Oscillator Options Clock ControlPLL Performance Clock Control Clock Speed Control Register ±9. PLL Performance ClkSpdCtrl register CPU RTO Oscillator Trim Adjustment Rtrim Register Read Only Applies to MSP50C614 Device OnlyClkSpdCtrl Value Copied Shaded Execution Timing Execution Timing Reduced Power Modes Reduced Power Modes Reduced Power Modes Reduced Power Modes Light MID Deep ±3. Programmable Bits Needed to Control Reduced Power Modes → deeper sleep … relatively less power → Component DeterminedBy Controls Deeper sleep … Relatively less power → Event Determined Global interrupt enable is SET Peripheral Functions I/O General-Purpose I/O PortsPort a Port B Port C Port D Port E Peripheral Functions Input Port F Dedicated Input Port F Totem-Pole Output Port G Dedicated Output Port G Internal and External Interrupts Branch on D Port Interrupt Vector Source Trigger Event Priority Comment ±1. Interrupts Pulse-Density Modulation Rate Digital-to-Analog Converter DACDAC Control and Data Registers Digital-to-Analog Converter DAC Overflow bits Least-significant data value Ignored bits ±1. PDM Clock Divider PDM Clock Divider Digital-to-Analog Converter DAC CPU Pllm Comparator TIMER1 starts counting For INT7 is enabledCleared. Refer to .7, Interrupt Logic, for more details Address Comparator Interrupt/General Control Register Interrupt/General Control RegisterIntGenCtrl register Interrupt/General Control Register Hardware Initialization States Hardware Initialization States Hardware Initialization States RZF Bit Bit Name Initialized Value DescriptionPage Assembly Language Instructions System Registers Introduction Assembly Language Instructions Top of Stack, TOSSystem Registers Product High Register PH Product Low Register PLAccumulators AC0±AC31 Accumulator Pointers AP0±AP3 Indirect Register R0±R7Bit Status Register Stat String Register STR Function ±1. Status Register Stat 1 MSP50P614/MSP50C614 Instruction Syntax Instruction Syntax and Addressing Modes Addressing Modes ±2. Addressing Mode EncodingOpcode Next a ±3. Rx Bit Description ±4. Addressing Mode Bits and adrs Field Description ±6. Auto Increment and Auto Decrement Modes ±5. MSP50P614/MSP50C614 Addressing Modes Summary Flag Repeat Flag addressing mode encoding, flagadrsFlagadrs Clocks Words Addressing Operation, ² Syntax Immediate Addressing SyntaxExample Direct Addressing MOV *0x012F * 2, *A0Mulr *0x02A1 Indirect Addressing ±9. Indirect Addressing SyntaxSyntaxOperation MOV A2, *R0 Relative Addressing*R4++ Movb *R7++, A3 Short Relative A0, *R3+R5 Long Relative MOV A3, *R6+0x10 TF1, *0x20 Flag AddressingOr TF2, *R6+0x02 XOR TF1, *R6+0x20 8 Tag/Flag Bits TF1,*ram1 TF1 bit in Stat is set!? Possible sources of confusion Consider the following code Symbol Explanation ±10. Symbols and ExplanationInstruction Classification Instruction Classification ±11. Symbols and Explanation ±11. Instruction ClassificationClass Sub- Description Class Sub Description Class 1 Instructions Memory and Accumulator Reference ±12. Classes and Opcode Definition ±14. Class 1a Instruction Description ±13. Class 1 Instruction EncodingC1a ~A~ C1b C1b Mnemonic Description ±15. Class 1b Instruction Description Shltpls a n, adrs Class 2 Instructions Accumulator and Constant Reference ±16. Class 2 Instruction Encoding ±17. Class 2a Instruction DescriptionC2a Mnemonic Description Class 3 Instruction Accumulator Reference ±18. Class 2b Instruction DescriptionC2b Mnemonic Description ADD An ~, An ~, imm16 , next a ±19. Class 3 Instruction Encoding ±20. Class 3 Instruction DescriptionMnemonic Description Zero or be set equal to the sign bit Xsgm dependent MOV SV, An~ , next a ±21. Class 4a Instruction Encoding Class 4 Instructions Address Register and Memory Reference ±23. Class 4b Instruction Description ±22. Class 4a Instruction Description±24. Class 4c Instruction Description ±25. Class 4d Instruction Description Class 5 Instructions Memory Reference ±26. Class 5 Instruction Encoding±27. Class 5 Instruction Description RET² ±28. Class 6a Instruction Encoding Class 6 Instructions Port and Memory Reference±29. Class 6a Instruction Description C6a Mnemonic Description ±30. Class 6b Instruction Description Class 7 Instructions Program ControlC6b Mnemonic Description Vector8 ±31. Class 7 Instruction Encoding and DescriptionJcc Ccc ±32. Class 8a Instruction Encoding Class 8 Instructions Logic and Bit ±34. Class 8b Instruction Description ±33. Class 8a Instruction DescriptionClass 9 Instructions Miscellaneous C8a Mnemonic Description ±36. Class 9a Instruction Description ±35. Class 9a Instruction Encoding±37. Class 9b Instruction Description C9a Mnemonic Description ±38. Class 9c Instruction Description Bit, Byte, Word and String Addressing±39. Class 9d Instruction Description C9c Mnemonic Description ±3. Data Memory Organization and Addressing ±40. Data Memory Address and Data Relationship Mode Address Used Data Order Rx Post modify ²Movb A0, *0x0003 MOV A0, *0x0004 Which uses the absolute word memory address ±4. Data Memory Example Rflag MSP50P614/MSP50C614 Computational Modes MSP50P614/MSP50C614 Computational Modes ±41. MSP50P614/MSP50C614 Computational Modes Computational Setting Resetting Function Mode Instruction SXM Example 4.6.1 Sovm Example 4.6.2 SovmExample 4.6.1 SXM Hardware Loop Instructions Hardware Loop Instructions Syntax Operation Limitations ±42. Hardware Loops in MSP50P614/MSP50C614 ±43. Initial Processor State for String Instructions String InstructionsString Instructions Registers register# = value Mulapl A0, A0~ ±44. Lookup Instructions Lookup InstructionsLookup Instructions Instructions Description Data Transfer MOV An, adrs SUB An MOV An, *An Special Filter Instructions Input/Output InstructionsInput/Output Instructions Xk±2 Xk+2 Xk±1 xk+1 32 or Yk = Σm =0..N hm⋅xk-m Special Filter Instructions STR,N±2 STR,0 0x0104 After FIR/COR execution Important note about setting the Stat register Firkcoeffs Coeffarray Samplebuf address Coeffarray address FIRK/CORK only Program memory FIRK/CORKFIR/COR only = 0..N Coeffarray Samplebuf Coeffarray is stored Conditionals Conditionals Operands Symbol Meaning≤ dma6 ≤ ≤ dma16 ≤ ≤ port4 ≤ ≤ port6 ≤ Clk AdrsnDma n Flg Offset n Pma nPort n ±46. Addressing Mode Bits and adrs Field Description ±45. Auto Increment and Decrement±47. Flag Addressing Syntax and BIts Individual Instruction Descriptions Individual Instruction Descriptions Execution 14.1 ADD Add word See Also Description Addb PC PC + Flags AffectedOpcode Clock , clk Words , w Adds Add String Adds A1, A1~, A1 14.4 Bitwise ANDS, ANDB, OR, ORB, ORS, XOR, XORB, Xors A3, *R4Ð±TF2, *0x0020 Src byte PC PC + Andb Bitwise and ByteOF, SF, ZF, CF are set accordingly Clock , clk Word , w Ands A0, A0~, A0 Ands Bitwise and StringAnds A0, A0~, *R2 Clock, clk Word, w Save next instruction address PC + Begloop Begin LoopFlags Affected None Opcode Order to loop N times Call Unconditional Subroutine Call TOS PC + TOSR7 + NOP True condition Not true condition ±48. Names for cc Syntax Alternate Syntax Description 0x2010 CALL, VCALL, RET, IretCTF1 Crnbe Stat flags set by src ± src1 operation 14.10 CMP Compare Two WordsPC = PC + w CMPB, CMPS, Jcc, Ccc CMP R0, R5 CMP R2, 0xfe20 Cmpb R3 Cmpb Compare Two Bytes PC PC + w Flags Affected Cmps Compare Two StringsCmps A1~ Cmps A2, A2~ 3n R+2 14.13 COR Correlation Filter FunctionXeven = R xeven + R5 Xeven ++ Sample data. During Cork execution, interrupt is queued Cork Correlation Filter FunctionAn, *Rx 3nR+2 Rxeven = Rxeven + R5 Decrement R4 by n 1 or First address after Begloop Else Endloop End LoopArgument, it assumes n =1 BEGLOOP, Inte An~ , next a Extsgn Sign Extend WordCopy accumulator sign flag SF to all 16 bits of An~ Dest , mod Extsgns Sign Extend String Extsgn 2n R+2 14.18 FIR FIR Filter Function Coefficients in RAM Assembly Language Instructions 101 Firk Be even. During Firk execution, interrupts are queuedRPT, FIR, COR, Cork Assembly Language Instructions 103 Idle Halt ProcessorStop processor clocks 14.21 Input From Port Into Word INS, OUT, OutsA2~, 0x3d IN, OUT, Outs 14.22 INS Input From Port Into String IM is Stat bit Intd Interrupt DisableStat to INTE, Iret Inte Interrupt Enable Assembly Language Instructions 107INTD, Iret R7 R7 ± Iret Return From InterruptSee Also RET, CALL, C cc, INTE, Intd Description Return from interrupt. Pop top of stack to program counter PC PC + 14.26 Jcc Conditional Jumps 110 If test condition is false, a NOP is executed JNZ See Also JMP, CALL, C cc ExampleJE 0x2010, R3++R5 JIN1 0x2010, R1±± Post±modify Rx if specified 14.27 JMP Unconditional JumpRCF and RZF affected by post±modification of Rx See Also Jcc, CALL, Ccc Example 14.28 MOV Move Data Word From Source to Destination Clock, clk Word, w With RPT, clk Class XSF, XZF are set accordinglyTFn, cc , Rx STR, imm8 116 With some operand types Example 4.14.28.10 MOV MR, A3, ±±A MOVU, MOVT, MOVB, MOVBS, MovsExample 4.14.28.11 MOV A1~, *A1 Example 4.14.28.12 MOV *0x0200 * 2, R0 Example 4.14.28.15 MOV *0x0200 * 2, R0 Example 4.14.28.13 MOV R1, 0x0200Transfer R5 to R0 Example Example 4.14.28.18 MOV *R6 + 8 * 2, DP Movaph Move With Adding PH Execution + PHMOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs Execution An + PH Movaphs Move With Adding PHBackground. See .8 for more details MOVAPH, MOVTPH, MOVTPHS, MOVSPH, Movsphs Copy value of unsigned src byte to dest byte Movb Move Byte From Source to DestinationMovb A0, *R2 Copy data memory byte pointed by R2 to accumulator A0 Movb *R2, A0 Movb A0, 0xf2Movb R2 TAG bit is set to bit 17 th value Movbs Move Byte String from Source to DestinationMovbs A2, *0x0200 Movbs *0x0200, A2 Movs Move String from Source to Destination Movs A2~ Movs A1, A1~Movs A1~, A1 Assembly Language Instructions 127 MovsphMOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs Movsphs Move String With Subtract From PH Second word ± PH MR contents of adrsDetails MOVSPH, MOVAPH, MOVAPHS, MOVTPH, Movtphs PC PC + w Flags Affected None Opcode MovtAvailable MOVU, MOV, MOVT, MOVB, MOVBS, Movs TAG bit is set accordingly UM is set to Movu Move Data UnsignedMOV, MOVB, MOVT, MOVBS, Movs Copy the value pointed by R3 to MR Assembly Language Instructions 131 MR * src PC PC + w Flags Affected 14.38 MUL Multiply RoundedAccumulator pointer if specified MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, Mulapl Muls Multiply String With No Data Transfer Length nS+2, where nS is the value in STR registerPH,PL MR * src string MUL, MULR, MULAPL, MULSPL, MULSPLS, MULTPL, Multpls PH ,PL MR * src Mulapl Multiply and Accumulate ResultBackground. See .8 for more detail MULAPLS, MULSPL, MULSPLS, MULTPL, Multpls Mulapls Multiply String and Accumulate Result MR * srcMULAPL, MULSPL, MULSPLS, MULTPL, Multpls Occuring in the background. See .8 for more details Mulspl Multiply and Subtract PL From AccumulatorMULSPLS, MULTPL, MULTPLS, MULAPL, Mulapls Syntax Description Mulspl adrs From dest string Mulspls Multiply String and Subtract PL From AccumulatorMULSPL, MULTPL, MULTPLS, MULAPL, Mulapls Syntax Description Mulspls adrs Multpl Multiply and Transfer PL to Accumulator Execution PH, PL MR * src PC PC + Flags Affected MultplsStored in An string MULTPL, MULAPL, MULAPLS, MULSPL, Mulspls Accumulator Negac Twos Complement Negation of AccumulatorNEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs Example 4.14.46.1 Negac A3~, A3, ±±A Negacs Twos Complement Negation of Accumulator String Assembly Language Instructions 141Dest accumulator string NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs 14.48 NOP No Operation Execution PC PC +RPT NOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, Xors Notac Ones Complement Negation of AccumulatorNEGAC, Negacs Example 4.14.49.1 Notac A3~, A3, ±±A Accumulator string Notacs Ones Complement Negation of Accumulator StringNegacs A3~ 14.51 or Bitwise Logical or TFn bits in Stat register are set accordinglyAccumulator pointers are allowed with some operand types ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs Or A0, *R0++R5Or TF1, *R6+0x22 Or src 14.52 ORB Bitwise or ByteAccumulator is affected OR, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs PC + w Flags Affected 14.53 ORS Bitwise or StringOR, ORB, AND, ANDS, XOR, XORS, NOTAC, Notacs ORS A0, A0~, A0 14.54 OUT Address is multipled by 4 to get the actual port addressOUTS, IN, INS Port6 specified in the instruction Outs Output String to PortOUT, IN, INS Port6 , An ~ 14.56 RET Return From Subroutine CALL, Ccc Assembly Language Instructions 151PC TOS CALL, i.e., RET followed by a RET should not be allowed Rflag Reset Memory Flag Sflag , Stag , RtagExample 4.14.57.2 Rflag *R6 + Resets the fractional mode. Clears FM bit of Stat Reset Fractional Mode Syntax14.58 RFM STAT.FM Saturation output normal mode Rovm Reset Overflow ModeResets the overflow mode to zero Stat .OM Load src to repeat counter 14.60 RPT Repeat Next InstructionLoad imm8 to repeat counter After execution completes Stag , Rflag , Sflag Rtag Reset TagRtag *R6+0x0002 Rtag *R6+0x0003 Assembly Language Instructions 157 14.62 RXM Reset Extended Sign ModeSTAT.XM SXM Address flagadrs only accesses the 17 th bit Sflag Set Memory FlagRflag , Stag , Rtag Mode for signed fractional arithmetic 14.64 SFM Set Fractional ModeAssembly Language Instructions 159 Set fractional mode. Set FM bit of Stat to PH , PL 14.65 SHL Shift LeftAccumulator. Use Shlac for this purpose Shls Its offset. LSB of result is set to zero Shlac Shift Left AccumulatorShift accumulator A1 by one bit to the left Example 4.14.66.2 Shlac A1~, A1, ±±A Accumulators in the string Shlacs Shift Left Accumulator String Individually Example 4.14.68.1 Shlapl A0, *R4++R5 Shlapl Shift Left with AccumulateShlapl A2, *R1++ Example 4.14.68.3 Shlapl A1, A1, ++A Shlapls Shift Left String With Accumulate Shift data memory string left, add PL to a nShift a n ~ string left, addb PL to a n ~ Shls Shift Left Accumulator String to Product Assembly Language Instructions 165Execution PH, PL An~ Example 4.14.71.1 Shlspl A0, *R4++R5 Shlspl Shift Left With Subtract PLShlspl A2, *R1++ Example 4.14.71.3 Shlspl A1, A1, ++A Bit to the next accumulator Shlspls Shift Left String With Subtract PLShlspl , Shltpl , SHLTPLS, SHLAPL, Shlapls Syntax Description Shlspls An, adrs Example 4.14.73.1 Shltpl A0, *R4++R5 Shltpl Shift Left and Transfer PL to AccumulatorShltpl A2, *R1++ Example 4.14.73.3 Shltpl A1, A1, ++A Execution PH, PL src SV Shltpls Shift Left String and Transfer PL to AccumulatorReceives the same data as PH SHLTPL, SHLAPL, SHLAPLS, SHLSPL, Shlspls Register Shrac Shift Accumulator RightShift right one bit the accumulator A1 Example 4.14.75.2 Shrac A1~, A1, ++A Shracs Shift Accumulator String Right Assembly Language Instructions 171SHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, Shltpl Shltpls Output DSP mode Set Overflow Mode SyntaxSovm STAT.OM Stag RTAG, RFLAG, SflagStag *0x401 Dest, src , src1 , next a 14.79 SUB SubtractAn ~ , An , adrs , next a An ~ , An ~ , imm16 , next a SUB A1, A1~, A1 Example 4.14.79.2 SUB A0, A0, 2, ++ASUB A3~, A3, *R4Ð SUB R3, R5 Subtract 0x45 from accumulator A2 byte Subb Subtract ByteSubtract 0xF2 from register R3 byte Syntax Description Subb a n, imm8 Subs Subtract Accumulataor String Assembly Language Instructions 177 Subs A2, A2, A2~ Subs A2, A2~, A2Subs A3~, A3~, PH Sets extended sign mode status register Stat bit 0 to 14.82 SXM Set Extended Sign ModeAssembly Language Instructions 179 RXM Push PC + 0x7F00 Vcall Vectored CallR7 R7 + Flags Affected See Also RET, IRET, CALL, C cc Example XOR src For two operands 14.84 XOR Logical XORXOR src For three operands TAG bit is set accordingly Src is flagadrs XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Example 4.14.84.1 XOR A1, A1, 0x13FFExample 4.14.84.2 XOR A0, A0, 2, ++A Assembly Language Instructions 183 Xorb Logical XOR ByteXOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Dest string Xors Logical XOR StringXOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Xors A2, A2~, A2 Assembly Language Instructions 185 Reset the content of accumulator A0 to zero14.87 ZAC Zero Accumulator Zacs Zacs Zero Accumulator String Reset the content of offset accumulator string A1~ to zeroPC PC + Flags Affected ZF = Zero the specified accumulator string Assembly Language Instructions 187 Instruction Set EncodingInstruction Set Encoding 188 Assembly Language Instructions 189 190 Assembly Language Instructions 191 192 Assembly Language Instructions 193 194 True condition Not true condition Assembly Language Instructions 195 Instruction Set Summary An~, An~ , next a Pma16 , Rmod Assembly Language Instructions 197An~, imm16 , next a Rx, R5 ~, adrs , next a ±46 Adrs, a n~ , next a ±46Adrs , *An ±46 An ~, imm16 , next a Adrs, SV Assembly Language Instructions 199Adrs, APn Adrs, TOS ~ , next a MR, adrs~, a n~ , next a ~ , a n~ TFn, flagadrs NR+3 TFn, cc , Rx An~, An~ , next a NR+3 Assembly Language Instructions 201An~, An~, pma16 An~, An~, An ~, a n, a n~ , next a ~, a n~~, a n, a n~ ~, a n~, PH Conditional on RZF=0 and RCF=1 Not condition RZF≠0 or RCF≠1 Conditional on RCF=1 Not condition RCF=0Conditional on RZF=1 Not condition RZF=0 Conditional on ZF=0 and SF=1 Not condition ZF≠0 or SF≠1 Instruction Set Summay 204Assembly Language Instructions MC = Pllm value+1 ⋅ 131.07 kHz 206Assembly Language Instructions Summay Instruction Set Summay 208Assembly Language Instructions Code Development Tools Introduction MSP50C6xx Software Development Tool MSP50C6xx Software Development ToolCode Development Tools PC Requirements RequirementsDevelopment Requirements Requirements Hardware Installation Hardware Installation Software Installation Software Installation ±5. Setup Window ±6. Exit Setup Dialog ±8. Choose Destination Location Dialog ±9. Select Program Folder Dialog ±10. Copying Files ±11.Setup Complete Dialog Software Emulator Open ScreenSoftware Emulator ±13. Project Menu Projects ±15. File Menu Options ±16. MSP50P614/MSP50C614 Code Development Windows Description of Windows ±17. RAM Window ±18. CPU Window ±19. Program Window ±20. Hardware Breakpoint Dialog ±21. Inspect Dialog Debugging a Program ±23. I/O Ports Window ±24. Debug Menu Software Emulator ±25. Eprom Programming Dialog ±26. Trace Mode ±27. Init Menu Option Initializing Chip Emulator Options ±28. Options Menu Emulator Online Help System ±30. Windows Menu Options ±31. Context Sensitive Help System Known Differences, Incompatibilities, Restrictions Assembler Assembler DLLAssembler Assembler Directives Examples~ indicates bitwise complement #IFDEF #ELSE see #IF and #IFDEF #IFNDEF symbol Example #IFDEF symbol#ELSE #ENDIF Assembler Linker Linker C± ± Compiler Ierr=LINKMAIN sourcefile,exefile± ± Compiler Foreword Variable Types External ReferencesType Name Mnemonic Range Size in Bytes Example 4 C± ± Directives Defines a replacement string for a given stringWithout Arguments With Arguments Must be present to terminate a #ifdef or #ifndef directive See #if directive Include Files Initializations Function Prototypes and DeclarationsRAM Usage String Functions ±1. String Functions An example of the use of xferconst is Constant Functions Comparisons Implementation DetailsThis section is C± ± specific Signed comparison of a and b. a is in A0, b is in A0~ Unsigned comparison of a and b. a is in A0, b is in A0~ Assembly Vector Function Calls DivisionStack frame has the following structure Low Address High Address Cmmfunc bidonint i1,char *i2 is valid, but Programming ExampleOn Call On RET Ifteststringm2,0,lgm2,LTSN Programming Example, C ±± With Assembly Routines ±±±±±±±±±±±±±±± Addb R7,2 To C function return in cmmreturn ±±±±±±±±±±±±±± OldR5 Return Addr Param R7,R5 Stack data Param ±±±±±±±±±±±±±± To ASM function return External Provided Data Iprtc Implementation Details Nop ret Dummy interrupt routines Implementation Details Implementation Details Beware of Stack Corruption Reported Bugs With Code Development ToolBeware of Stack Corruption Page Applications Application Circuits Application Circuits MSP50P614 only 100 kΩ MSP50C614/MSP50P614 Initialization Codes MSP50C614/MSP50P614 Initialization Codes File init.asm Begloop ~,TIM2REFOSC + TIM2IMR Overview Texas Instruments C614 Synthesis CodeGetting Started Texas Instruments C614 Synthesis Code Directory Structure Running the Program Spkram.irx ROM File Description Adding Another Module RAM UsageUnderstanding the RAM Map Modifying Files and Projects These files may be edited for special purpose code Memory OverlayThese files should never be edited Creating a New Project ROM Usage With Respect to Various Synthesis Algorithms ROM Usage With Respect to Various Synthesis Algorithms Customer Information Mechanical Information Die Bond-Out CoordinatesMechanical Information Customer Information Package Information ±1 -Pin PJM Mechanical Information ±2 -Pin Grid Array Package for the Development Device, P614 ±3 Pin Grid Array PGA Package Leads, P614 Customer Information Fields in the ROM Customer Information Fields in the ROM Speech Development Cycle Device Production SequenceSpeech Development Cycle Nprf Device Production Sequence New Product Release Forms Ordering InformationOrdering Information 614 New Product Release Forms Authorization to Generate MASKS, PROTOTYPES, and Risk UnitsPage MSP50C605 Preliminary Data Introduction Features Architecture Features ArchitecturePort Name IO Location MSP50C614 MSP50C605 1 RAM 3 I/O Pins2 ROM Port Description Function Name Address Figure A±1. MSP50C605 Architecture Data Memory Program MemoryData ROM Peripheral Ports Plastic Package Description Pin# Page MSP50C604 Preliminary Data Introduction Features Architecture Packaging Introduction MSP50C604 Preliminary Data Figure B±1. MSP50C604 Block Diagram Slave Mode Operation Host Write SequenceHost Read Sequence Program Memory Data MemoryPeripheral Ports Interrupts Packaging Packaging Plastic Package Packaging Topic MSP50C605 Data Sheet MSP50C605 Data Sheet