C0H, PRE1 PRE0 PRE2, WDR1, WDR2 WDS | Analog Devices ADuC812

ADuC812

WATCHDOG TIMER

The purpose of the watchdog timer is to generate a device reset within a reasonable amount of time if the ADuC812 enters an erroneous state, possibly due to a programming error.

The Watchdog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR. When enabled, the watchdog circuit will generate a system reset if the user program fails to set the watchdog timer refresh bits (WDR1, WDR2) within a predetermined amount of time (see PRE2–0 bits in WDCON).

The watchdog timer itself is a 16-bit counter. The watchdog timeout interval can be adjusted via the PRE2–0 bits in WDCON. Full Control and Status of the watchdog timer function can be controlled via the watchdog timer control SFR (WDCON).

WDCON	Watchdog Timer Control Register
SFR Address	C0H
Power-On Default Value	00H
Bit Addressable	Yes

PRE2

PRE1

PRE0

—

WDR1

WDR2

WDS

WDE

Table IX. WDCON SFR Bit Designations

Bit	Name	Description

7	PRE2	Watchdog Timer Prescale Bits.
6	PRE1
5	PRE0
		PRE2	PRE1	PRE0	Timeout Period (ms)
		0	0	0	16
		0	0	1	32
		0	1	0	64
		0	1	1	128
		1	0	0	256
		1	0	1	512
		1	1	0	1024
		1	1	1	2048
4	—	Not Used.
3	WDR1	Watchdog timer refresh bits, set sequentially to refresh the watchdog.
2	WDR2
1	WDS	Watchdog Status Bit.
		Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.
		Cleared by writing a “0” or by an external hardware reset. It is not cleared by a watchdog reset.
1	WDE	Watchdog Enable Bit.
		Set by user to enable the watchdog and clear its counters.

Example

To set up the watchdog timer for a timeout period of 2048 ms the following code would be used.

MOV	WDCON,#0E0h	;2.048 second
		;timeout period
SETB	WDE	;enable watchdog timer

In order to prevent the watchdog timer timing out the timer refresh bits need to be set before 2.048 seconds has elapsed.

SETB	WDR1	;refresh watchdog timer..
SETB	WDR2	; ..bits must be set in this
		;order

–24–

REV. B

Image 24

Analog Devices ADuC812 manual C0H, PRE1 PRE0 PRE2, WDR1, WDR2 WDS, Wde

Contents

Functional Block Diagram General Description Table of Contents ADuC812 ADC Channel Specifications DC ACCURACY3 Calibrated Endpoint ERRORS5Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11 DAC AC Characteristics FLASH/EE Memory Performance CHARACTERISTICS12Watchdog Timer Characteristics Power Supply Monitor Characteristics Power REQUIREMENTS14, 15 Digital OutputsIsource = 80 ∝A Isource = 20 ∝A Temperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function ADC Specifications DAC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dB ARCHITECTURE, Main Features Memory Organization Bit Name Description Default Value SFR Address SFR Notes Special Function Registers ADC Circuit Information General OverviewADC Transfer Function Typical Operation EFH AQ1AQ0 #ADC Clks ADCCON1.1 T2C Location Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections Where the ADC Results are to be written. This is done by External memory must be preconfigured. This consistsDMAP. Dmal must be written to first, followed by Dmah and then by Dmap SFR area Byte Program SequenceNonvolatile Flash Memory Econ B9HEadrl C6H Command Byte Command Mode FDH ModeRNG1 RNG0 Using the D/A Converter Resistor String DAC Functional Equivalent Source and Sink Current Capability with Vref = VDD = 3 C0H PRE2PRE1 PRE0 PRE2 WDR1 DFH DCHCMP Psmi F8H OOHIspi Wcol SPR1 SPR0SPR1 SPR0 F7H I2CCON 2C Control Register Pin Alternate Function Compatible ON-CHIP Peripherals TMOD, Tcon T2CON TF1 TR1TF0 TR0 TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter C8H TF2EXF2 Rclk CAP2 TR2 Mode Rclk or TclkOFF SM0 SM1SM0 SM1 SM2 Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L A8H EadcET2 ET1 Source Priority Description Source Vector Address ADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface Down to 1.2 V or less. The timing diagram of illus ADuC812-based system as well as during its normal power-onLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendations Normal Mode Idle ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk + Grounding and Board Layout Recommendations System Grounding Schemes In-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger Quickstart Development System ADSIM-Windows Simulator XTAL1 Period 83.33 62.5 1000 XTAL1 Width LowXTAL1 Width High XTAL1 Rise Time 12 MHz Variable Clock Parameter Min Max Unit External Program Memory External Data Memory Read Cycle External Data Memory Write Cycle Output Data Setup to Clock 700 10t CK Input Data Setup to Clock 300 2t CK +Serial Port Clock Cycle Time 12t CK Input Data Hold after Clock Parameter Min Max Unit I2C-COMPATIBLE Interface Timing SPI Master Mode Timing Cpha = Parameter Min Typ Max Unit Data Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Entire Data Sheet has been revised Outline DimensionsLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack