Source Priority Description | Analog Devices ADuC812 guide

ADuC812

IE2:	Secondary Interrupt Enable Register
SFR Address	A9H
Power-On Default Value	00H
Bit Addressable	No

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EPSMI

ESI

		Table XXV. IE2 SFR Bit Designations

Bit	Name	Description

7	—	Reserved for Future Use.
6	—	Reserved for Future Use.
5	—	Reserved for Future Use.
4	—	Reserved for Future Use.
3	—	Reserved for Future Use.
2	—	Reserved for Future Use.
1	EPSMI	Written by User to Enable “1” or Disable “0” Power Supply Monitor Interrupt.
0	ESI	Written by User to Enable “1” or Disable “0” SPI/I2C Serial Port Interrupt.

Interrupt Priority

The Interrupt Enable registers are written by the user to enable individual interrupt sources, while the Interrupt Priority registers allow the user to select one of two priority levels for each interrupt. An interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt will be serviced first. An interrupt cannot be interrupted by another interrupt of the same priority level. If two interrupts of the same priority level occur simultaneously, a polling sequence is observed as shown in Table XXVI.

Table XXVI. Priority within an Interrupt Level

Source	Priority		Description

PSMI	1	(Highest)	Power Supply Monitor Interrupt
IE0	2		External Interrupt 0
ADCI	3		ADC Interrupt
TF0	4		Timer/Counter 0 Interrupt
IE1	5		External Interrupt 1
TF1	6		Timer/Counter 1 Interrupt
I2CI + ISPI	7		I2C/SPI Interrupt
RI + TI	8		Serial Interrupt
TF2 + EXF2	9	(Lowest)	Timer/Counter 2 Interrupt

Interrupt Vectors

When an interrupt occurs the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The interrupt Vector Addresses are shown in the Table XXVII.

Table XXVII. Interrupt Vector Addresses

Source	Vector Address

IE0	0003 Hex
TF0	000B Hex
IE1	0013 Hex
TF1	001B Hex
RI + TI	0023 Hex
TF2 + EXF2	002B Hex
ADCI	0033 Hex
I2CI + ISPI	003B Hex
PSMI	0043 Hex

REV. B

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Analog Devices ADuC812 manual Source Priority Description, Source Vector Address

Contents

General Description Functional Block Diagram ADuC812 Table of Contents DAC Channel Specifications DC ACCURACY11 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 Temperature SENSOR10 Power Supply Monitor Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Watchdog Timer Characteristics Isource = 20 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 80 ∝A Temperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function Thus for a 12-bit converter, this is 74 dB ADC SpecificationsDAC Specifications Terminology Memory Organization ARCHITECTURE, Main Features Bit Name Description Special Function Registers Default Value SFR Address SFR Notes Typical Operation ADC Circuit InformationGeneral Overview ADC Transfer Function ADCCON1.1 T2C EFHAQ1 AQ0 #ADC Clks Location Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections Dmah and then by Dmap Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists DMAP. Dmal must be written to first, followed by SFR area Byte Program SequenceNonvolatile Flash Memory C6H EconB9H Eadrl Command Byte Command Mode RNG0 FDHMode RNG1 Resistor String DAC Functional Equivalent Using the D/A Converter Source and Sink Current Capability with Vref = VDD = 3 WDR1 C0HPRE2 PRE1 PRE0 PRE2 Psmi DFHDCH CMP Wcol F8HOOH Ispi F7H SPR1SPR0 SPR1 SPR0 2C Control Register I2CCON Compatible ON-CHIP Peripherals Pin Alternate Function T2CON TMOD, Tcon TR0 TF1TR1 TF0 TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter Rclk C8HTF2 EXF2 CAP2 TR2 Mode Rclk or TclkOFF SM2 SM0SM1 SM0 SM1 Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L ET1 A8HEadc ET2 Source Vector Address Source Priority Description ADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface High it tracks the voltage on DVDD. These recommendations Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on Level. The external POR circuit must be operational Core NAs ⋅ Mclk + Normal ModeIdle Mode VDD = 5 VDD = 3 System Grounding Schemes Grounding and Board Layout Recommendations In-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development System XTAL1 Rise Time XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Width High External Program Memory 12 MHz Variable Clock Parameter Min Max Unit External Data Memory Read Cycle External Data Memory Write Cycle Input Data Hold after Clock Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Serial Port Clock Cycle Time 12t CK I2C-COMPATIBLE Interface Timing Parameter Min Max Unit Parameter Min Typ Max Unit SPI Master Mode Timing Cpha = Data Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Lead Plastic Quad Flatpack Entire Data Sheet has been revisedOutline Dimensions Location Data Sheet changed from REV. a to REV. B