REV. B
ADuC812
–11–
SPECIAL FUNCTION REGISTERS
All registers except the program counter and the four general purpose register banks, reside in the special function register (SFR)area. The SFR registers include control, configuration and data registers that provide an interface between the CPU and other on-chip peripherals.Figure 4 shows a full SFR memory map and SFR contents on Reset. Unoccupied SFR locations are shown dark-shaded in the figurebelow (NOT USED). Unoccupied locations in the SFR address space are not implemented i.e., no register exists at this location. Ifan unoccupied location is read, an unspecified value is returned. SFR locations reserved for on chip testing are shown lighter shadedbelow (RESERVED) and should not be accessed by user software. Sixteen of the SFR locations are also bit addressable and denotedby'1'
in the figure below, i.e., the bit addressable SFRs are those whose address ends in 0H or 8H.SPICON
1
F8H 00H
DAC0L
F9H 00H
DAC0H
FAH 00H
DAC1L
FBH 00H
DAC1H
FCH 00H
DACCON
FDH 04H
RESERVED NOT USED
B
1
F0H 00H
ADCOFSL
3
F1H 00H
ADCOFSH
3
F2H 20H
ADCGAINL
3
F3H 00H
ADCGAINH
3
F4H 00H
ADCCON3
F5H 00H
RESERVED
I2CCON
1
E8H 00H
RESERVED
ACC
1
E0H 00H
RESERVED
ADCCON2
1
D8H 00H
ADCDATAL
D9H 00H
ADCDATAH
DAH 00H
RESERVED
PSW
1
D0H 00H
DMAL
D2H 00H
DMAH
D3H 00H
DMAP
D4H 00H
RESERVED
T2CON
1
C8H 00H
RCAP2L
CAH 00H
RCAP2H
CBH 00H
TL2
CCH 00H
TH2
CDH 00H
RESERVED
WDCON
1
C0H 00H
IP
1
B8H 00H
ECON
B9H 00H
ETIM1
BAH 52H
ETIM2
BBH 04H
EDATA1
BCH 00H
EDATA2
BDH 00H
NOT USED
IE
1
A8H 00H
IE2
A9H 00H
NOT USED
P2
1
A0H FFH
NOT USED
SCON
1
98H 00H
SBUF
99H 00H
I2CDAT
9AH 00H
I2CADD
9BH 55H
NOT USED
P1
1, 2
90H FFH
NOT USED
TCON
1
88H 00H
TMOD
89H 00H
TL0
8AH 00H
TL1
8BH 00H
TH0
8CH 00H
TH1
8DH 00H
NOT USED
P0
1
80H FFH
SP
81H 07H
DPL
82H 00H
DPH
83H 00H
DPP
84H 00H
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
RESERVEDRESERVEDRESERVED
RESERVEDRESERVEDRESERVED
RESERVED
RESERVEDRESERVED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USEDNOT USEDNOT USEDNOT USEDNOT USEDNOT USED
P3
1
B0H FFH
NOT USEDNOT USEDNOT USEDNOT USED
NOT USEDNOT USEDNOT USEDNOT USEDNOT USED
NOT USEDNOT USEDNOT USEDNOT USEDNOT USED
NOT USEDNOT USEDNOT USED
SPIDAT
F7H 00H
ADCCON1
EFH 20H
RESERVED
PSMCON
DFH DEH
EDARL
C6H 00H
EDATA3
BEH 00H
EDATA4
BFH 00H
NOT USEDNOT USED
PCON
87H 00H
ISPI
FFH 0
WCOL
FEH 0
SPE
FDH 0
SPIM
FCH 0
CPOL
FBH 0
CPHA
FAH
SPR1
F9H 0
SPR0
F8H 0
BITS
F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H F1H 0 F0H 0
BITS
MDO
EFH 0
MDE
EEH 0
MCO
EDH 0
MDI
ECH 0
I2CM
EBH 0
I2CRS
EAH
I2CTX
E9H 0
I2CI
E8H 0
BITS
E7H 0 E6H 0 E5H 0 E4H 0 E3H 0 E2H E1H 0 E0H 0
BITS
ADCI
DFH 0
DMA
DEH 0
CCONV
DDH 0
SCONV
DCH 0
CS3
DBH 0
CS2
DAH
CS1
D9H 0
CS0
D8H 0
BITS
CY
D7H 0
AC
D6H 0
F0
D5H 0
RS1
D4H 0
RS0
D3H 0
OV
D2H
FI
D1H 0
P
D0H 0
BITS
TF2
CFH 0
EXF2
CEH 0
RCLK
CDH 0
TCLK
CCH 0
EXEN2
CBH 0
TR2
CAH
CNT2
C9H 0
CAP2
C8H 0
BITS
PRE2
C7H 0
PRE1
C6H 0
PRE0
C5H 0 C4H 0
WDR1
C3H 0
WDR2
C2H
WDS
C1H 0
WDE
C0H 0
BITS
PSI
BFH 0
PADC
BEH 0
PT2
BDH 0
PS
BCH 0
PT1
BBH 0
PX1
BAH
PT0
B9H 0
PX0
B8H 0
BITS
RD
B7H 1
WR
B6H 1
T1
B5H 1
T0
B4H 1
INT1
B3H 1
INT0
B2H
TxD
B1H 1
RxD
B0H 1
BITS
EA
AFH
EADC
AEH
ET2
ADH
ES
ACH 0
ET1
ABH 0
EX1
AAH
ET0
A9H 0
EX0
A8H 0
BITS
A7H A6H A5H 1 A4H 1 A3H 1 A2H A1H 1 A0H 1
BITS
SM0
9FH 0
SM1
9EH 0
SM2
9DH 0
REN
9CH 0
TB8
9BH 0
RB8
9AH
TI
99H 0
RI
98H 0
BITS
97H 1 96H 1 95H 1 94H 1 93H 1 92H
T2EX
91H 1
T2
90H 1
BITS
TF1
8FH 0
TR1
8EH 0
TF0
8DH 0
TR0
8CH 0
IE1
8BH 0
IT1
8AH
IE0
89H 0
IT0
88H 0
BITS
87H 1 86H 1 85H 1 84H 1 83H 1 82H 81H 1 80H 1
BITS
1
1
0
1
0
1
IE0
89H 0
IT0
88H 0
TCON
88H 00H
MNEMONIC
SFR ADDRESS
DEFAULT VALUE
MNEMONIC
DEFAULT VALUE
SFR ADDRESS
THESE BITS ARE CONTAINED IN THIS BYTE.
SFR MAP KEY:
SFR NOTES:
1
SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE.
2
THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT; THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS ON THESE
PORT PINS, WRITE A '0' TO THE CORRESPONDING PORT 1 SFR BIT.
3
CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES.
0
RESERVEDRESERVED
RESERVED
ETIM3
C4H C9H
0
0
0
0
0
0
0
0
0
000
11