Analog Devices ADuC812 ADuC812

REV. B

ADuC812

–12–

ADC CIRCUIT INFORMATION

General Overview

The ADC conversion block incorporates a fast, 8-channel,

12-bit, single supply A/D converter. This block provides the

user with multichannel mux, track/hold, on-chip reference,

calibration features and A/D converter. All components in this

block are easily configured via a 3-register SFR interface.

The A/D converter consists of a conventional successive-

approximation converter based around a capacitor DAC. The

converter accepts an analog input range of 0 to +V

REF

. A high

precision, low drift and factory calibrated 2.5 V reference is

provided on-chip. The internal reference may be overdriven via

the external V

REF

pin. This external reference can be in the

range 2.3 V to AV

Single step or continuous conversion modes can be initiated in

software or alternatively by applying a convert signal to the an

external pin. Timer 2 can also be configured to generate a repeti-

tive trigger for ADC conversions. The ADC may be configured

to operate in a DMA Mode whereby the ADC block continu-

ously converts and captures samples to an external RAM space

without any interaction from the MCU core. This automatic

capture facility can extend through a 16 MByte external Data

Memory space.

The ADuC812 is shipped with factory programmed calibration

coefficients which are automatically downloaded to the ADC on

power-up ensuring optimum ADC performance. The ADC core

contains internal Offset and Gain calibration registers. A

software calibration routine is provided to allow the user to

overwrite the factory programmed calibration coefficients if

required, thus minimizing the impact of endpoint errors in the

user’s target system.

A voltage output from an On-Chip bandgap reference propor-

tional to absolute temperature can also be routed through the

front end ADC multiplexor (effectively a 9th ADC channel

input) facilitating a temperature sensor implementation.

ADC Transfer Function

The analog input range for the ADC is 0 V to V

REF

. For this

range, the designed code transitions occur midway between

successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,

5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight

binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when

REF

= 2.5 V. The ideal input/output transfer characteristic for

the 0 to V

REF

range is shown in Figure 5.

OUTPUT

CODE

111...111

111...110

111...101

111...100

000...011

000...010

000...001

000...000

1LSB +FS

–1LSB

VOLTAGE INPUT

1LSB =

4096

Figure 5. ADC Transfer Function

Typical Operation

Once configured via the ADCCON 1-3 SFRs (shown on the

following page) the ADC will convert the analog input and provide

an ADC 12-bit result word in the ADCDATAH/L SFRs. The top

4 bits of the ADCDATAH SFR will be written with the channel

selection bits so as to identify the channel result. The format of the

ADC 12 bit result word is shown in Figure 6.

CH–ID

TOP 4 BITS

HIGH 4 BITS OF

ADC RESULT WORD

LOW 8 BITS OF THE

ADC RESULT WORD

ADCDATAH SFR

ADCDATAL SFR

Figure 6. ADC Result Format