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Analog Devices ADuC812 manual Data Output Valid after SS Edge

Models: ADuC812

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ADuC812

Parameter

Min

Typ

Max

Unit

Figure

SPI SLAVE MODE TIMING (CPHA = 0)

tSS

SS to SCLOCK Edge

tSL

SCLOCK Low Pulsewidth

330

tSH

SCLOCK High Pulsewidth

330

tDAV

Data Output Valid after SCLOCK Edge

tDSU

Data Input Setup Time before SCLOCK Edge

100

tDHD

Data Input Hold Time after SCLOCK Edge

100

tDF

Data Output Fall Time

tDR

Data Output Rise Time

tSR

SCLOCK Rise Time

tSF

SCLOCK Fall Time

tDOSS

Data Output Valid after SS Edge

tSFS

SS High after SCLOCK Edge

tSFS

tSS

SCLOCK

(CPOL=0)

tSH

tSL

tSR

SCLOCK

(CPOL=1)

tDAV

tDOSS

tDF tDR

MISO

MSB

BIT 6 – 1

LSB

MOSI

MSB IN

BIT 6 – 1

LSB IN

tDSU tDHD

Figure 59. SPI Slave Mode Timing (CPHA = 0)

REV. B

–55–

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Analog Devices ADuC812 manual Data Output Valid after SS Edge

Contents

General Description Functional Block DiagramADuC812 Table of ContentsDAC Channel Specifications DC ACCURACY11 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 Temperature SENSOR10Power Supply Monitor Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Watchdog Timer CharacteristicsIsource = 20 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 80 ∝APIN Configuration Temperature Package Model Range Description OptionOrdering Guide Mnemonic Type Function Thus for a 12-bit converter, this is 74 dB ADC SpecificationsDAC Specifications TerminologyMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesTypical Operation ADC Circuit InformationGeneral Overview ADC Transfer FunctionADCCON1.1 T2C EFHAQ1 AQ0 #ADC ClksCS3 CS2 CS1 CS0 CH# Location Name DescriptionBit Location Status Description Driving the A/D Converter Op Amp Model CharacteristicsTable VI. Some Single-Supply Op Amps ADC DMA Mode Configuring the ADCVoltage Reference Connections Dmah and then by Dmap Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists DMAP. Dmal must be written to first, followed byByte Program Sequence SFR areaNonvolatile Flash Memory C6H EconB9H EadrlCommand Byte Command Mode RNG0 FDHMode RNG1Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 WDR1 C0HPRE2 PRE1 PRE0 PRE2Psmi DFHDCH CMPWcol F8HOOH IspiF7H SPR1SPR0 SPR1 SPR02C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR0 TF1TR1 TF0Mode 3 Two 8-Bit Timer/Counters TIMER/COUNTER 0 and 1 Operating ModesMode 1 16-Bit Timer/Counter Rclk C8HTF2 EXF2Rclk or Tclk CAP2 TR2 ModeOFF SM2 SM0SM1 SM0 SM1Baud rate in Mode 0 is fixed CLK SmodRCAP2H RCAP2L ET1 A8HEadc ET2Source Vector Address Source Priority DescriptionClock Oscillator ADuC812 Hardware Design ConsiderationsExternal Memory Interface High it tracks the voltage on DVDD. These recommendations Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on Level. The external POR circuit must be operationalCore NAs ⋅ Mclk + Normal ModeIdle Mode VDD = 5 VDD = 3System Grounding Schemes Grounding and Board Layout RecommendationsOther Hardware Considerations In-Circuit Serial Download AccessEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Rise Time XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Width HighExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Hold after Clock Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Serial Port Clock Cycle Time 12t CKI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SS to Sclock Edge SPI Slave Mode Timing Cpha =SS High after Sclock Edge Data Output Valid after SS Edge Lead Plastic Quad Flatpack Entire Data Sheet has been revisedOutline Dimensions Location Data Sheet changed from REV. a to REV. B