TMOD, Tcon, T2CON | Analog Devices ADuC812 manual

ADuC812

User configuration and control of all Timer operating modes is achieved via three SFRs, namely:

TMOD, TCON:	Control and configuration for
	Timers 0 and 1.
T2CON:	Control and configuration for
	Timer 2.

TMOD	Timer/Counter 0 and 1 Mode
	Register
SFR Address	89H
Power-On Default Value	00H
Bit Addressable	No

Gate

C/T

M1

M0

Gate

C/T

M1

M0

			Table XVI. TMOD SFR Bit Designations

Bit	Name	Description

7	Gate	Timer 1 Gating Control.
		Set by software to enable timer/counter 1 only while INT1 pin is high and TR1 control bit is set.
		Cleared by software to enable timer 1 whenever TR1 control bit is set.
6	C/T	Timer 1 Timer or Counter Select Bit.
		Set by software to select counter operation (input from T1 pin).
		Cleared by software to select timer operation (input from internal system clock).
5	M1	Timer 1 Mode Select Bit 1 (Used with M0 Bit).
4	M0	Timer 1 Mode Select Bit 0.
		M1	M0
		0	0	TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
		0	1	16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
		1	0	8-Bit Auto-Reload Timer/Counter. TH1 holds a value which is to be
				reloaded into TL1 each time it overflows.
		1	1	Timer/Counter 1 Stopped.
3	Gate	Timer 0 Gating Control.
		Set by software to enable timer/counter 0 only while INT0 pin is high and TR0 control bit is set.
		Cleared by software to enable Timer 0 whenever TR0 control bit is set.
2	C/T	Timer 0 Timer or Counter Select Bit.
		Set by software to select counter operation (input from T0 pin).
		Cleared by software to select timer operation (input from internal system clock).
1	M1	Timer 0 Mode Select Bit 1.
0	M0	Timer 0 Mode Select Bit 0.
		M1	M0
		0	0	TH0 operates as an 8-bit timer/counter. TL0 serves as 5-bit prescaler.
		0	1	16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no
				prescaler
		1	0	8-Bit Auto-Reload Timer/Counter. TH0 holds a value which is to
				be reloaded into TL0 each time it overflows.
		1	1	TL0 is an 8-bit timer/counter controlled by the standard timer 0 control
				bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits.

–30–

REV. B

Image 30

Analog Devices ADuC812 manual TMOD, Tcon, T2CON

Contents

Functional Block Diagram General Description Table of Contents ADuC812 Temperature SENSOR10 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 DAC Channel Specifications DC ACCURACY11 Watchdog Timer Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Power Supply Monitor Characteristics Isource = 80 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 20 ∝A Temperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function Terminology ADC SpecificationsDAC Specifications Thus for a 12-bit converter, this is 74 dB ARCHITECTURE, Main Features Memory Organization Bit Name Description Default Value SFR Address SFR Notes Special Function Registers ADC Transfer Function ADC Circuit InformationGeneral Overview Typical Operation AQ0 #ADC Clks EFHAQ1 ADCCON1.1 T2C Location Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections DMAP. Dmal must be written to first, followed by Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists Dmah and then by Dmap SFR area Byte Program SequenceNonvolatile Flash Memory Eadrl EconB9H C6H Command Byte Command Mode RNG1 FDHMode RNG0 Using the D/A Converter Resistor String DAC Functional Equivalent Source and Sink Current Capability with Vref = VDD = 3 PRE1 PRE0 PRE2 C0HPRE2 WDR1 CMP DFHDCH Psmi Ispi F8HOOH Wcol SPR1 SPR0 SPR1SPR0 F7H I2CCON 2C Control Register Pin Alternate Function Compatible ON-CHIP Peripherals TMOD, Tcon T2CON TF0 TF1TR1 TR0 TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter EXF2 C8HTF2 Rclk CAP2 TR2 Mode Rclk or TclkOFF SM0 SM1 SM0SM1 SM2 Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L ET2 A8HEadc ET1 Source Priority Description Source Vector Address ADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface Level. The external POR circuit must be operational Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on High it tracks the voltage on DVDD. These recommendations VDD = 5 VDD = 3 Normal ModeIdle Mode Core NAs ⋅ Mclk + Grounding and Board Layout Recommendations System Grounding Schemes In-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger Quickstart Development System ADSIM-Windows Simulator XTAL1 Width High XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Rise Time 12 MHz Variable Clock Parameter Min Max Unit External Program Memory External Data Memory Read Cycle External Data Memory Write Cycle Serial Port Clock Cycle Time 12t CK Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Input Data Hold after Clock Parameter Min Max Unit I2C-COMPATIBLE Interface Timing SPI Master Mode Timing Cpha = Parameter Min Typ Max Unit Data Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Location Data Sheet changed from REV. a to REV. B Entire Data Sheet has been revisedOutline Dimensions Lead Plastic Quad Flatpack