Parameter Min Typ Max Unit | Analog Devices ADuC812 specification

ADuC812

Parameter		Min	Typ	Max	Unit	Figure

SPI MASTER MODE TIMING (CPHA = 1)
tSL	SCLOCK Low Pulsewidth		330		ns	57
tSH	SCLOCK High Pulsewidth		330		ns	57
tDAV	Data Output Valid after SCLOCK Edge			50	ns	57
tDSU	Data Input Setup Time before SCLOCK Edge	100			ns	57
tDHD	Data Input Hold Time after SCLOCK Edge	100			ns	57
tDF	Data Output Fall Time		10	25	ns	57
tDR	Data Output Rise Time		10	25	ns	57
tSR	SCLOCK Rise Time		10	25	ns	57
tSF	SCLOCK Fall Time		10	25	ns	57

SCLOCK (CPOL=0)

SCLOCK (CPOL=1)

MOSI

MISO

tSH

tDAV

tSL

tDF

MSB

MSB IN

tSRtSF

tDR

BIT 6 – 1	LSB
BIT 6 – 1	LSB IN

tDSU tDHD

Figure 56. SPI Master Mode Timing (CPHA = 1)

–52–

REV. B

Page 52

Image 52

Analog Devices ADuC812 manual Parameter Min Typ Max Unit, SPI Master Mode Timing Cpha =

Contents

Functional Block Diagram General Description Table of Contents ADuC812 ADC Channel Specifications DC ACCURACY3 Calibrated Endpoint ERRORS5Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11 DAC AC Characteristics FLASH/EE Memory Performance CHARACTERISTICS12Watchdog Timer Characteristics Power Supply Monitor Characteristics Power REQUIREMENTS14, 15 Digital OutputsIsource = 80 ∝A Isource = 20 ∝A PIN Configuration Temperature Package Model Range Description OptionOrdering Guide Mnemonic Type Function ADC Specifications DAC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dB ARCHITECTURE, Main Features Memory Organization Bit Name Description Default Value SFR Address SFR Notes Special Function Registers ADC Circuit Information General OverviewADC Transfer Function Typical Operation EFH AQ1AQ0 #ADC Clks ADCCON1.1 T2C CS3 CS2 CS1 CS0 CH# Location Name DescriptionBit Location Status Description Driving the A/D Converter Op Amp Model CharacteristicsTable VI. Some Single-Supply Op Amps ADC DMA Mode Configuring the ADCVoltage Reference Connections Where the ADC Results are to be written. This is done by External memory must be preconfigured. This consistsDMAP. Dmal must be written to first, followed by Dmah and then by Dmap Byte Program Sequence SFR areaNonvolatile Flash Memory Econ B9HEadrl C6H Command Byte Command Mode FDH ModeRNG1 RNG0 Using the D/A Converter Resistor String DAC Functional Equivalent Source and Sink Current Capability with Vref = VDD = 3 C0H PRE2PRE1 PRE0 PRE2 WDR1 DFH DCHCMP Psmi F8H OOHIspi Wcol SPR1 SPR0SPR1 SPR0 F7H I2CCON 2C Control Register Pin Alternate Function Compatible ON-CHIP Peripherals TMOD, Tcon T2CON TF1 TR1TF0 TR0 Mode 3 Two 8-Bit Timer/Counters TIMER/COUNTER 0 and 1 Operating ModesMode 1 16-Bit Timer/Counter C8H TF2EXF2 Rclk Rclk or Tclk CAP2 TR2 ModeOFF SM0 SM1SM0 SM1 SM2 Baud rate in Mode 0 is fixed CLK SmodRCAP2H RCAP2L A8H EadcET2 ET1 Source Priority Description Source Vector Address Clock Oscillator ADuC812 Hardware Design ConsiderationsExternal Memory Interface Down to 1.2 V or less. The timing diagram of illus ADuC812-based system as well as during its normal power-onLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendations Normal Mode Idle ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk + Grounding and Board Layout Recommendations System Grounding Schemes Other Hardware Considerations In-Circuit Serial Download AccessEmbedded Serial Port Debugger Quickstart Development System ADSIM-Windows Simulator XTAL1 Period 83.33 62.5 1000 XTAL1 Width LowXTAL1 Width High XTAL1 Rise Time 12 MHz Variable Clock Parameter Min Max Unit External Program Memory External Data Memory Read Cycle External Data Memory Write Cycle Output Data Setup to Clock 700 10t CK Input Data Setup to Clock 300 2t CK +Serial Port Clock Cycle Time 12t CK Input Data Hold after Clock Parameter Min Max Unit I2C-COMPATIBLE Interface Timing SPI Master Mode Timing Cpha = Parameter Min Typ Max Unit Data Output Setup before Sclock Edge 150 SS to Sclock Edge SPI Slave Mode Timing Cpha =SS High after Sclock Edge Data Output Valid after SS Edge Entire Data Sheet has been revised Outline DimensionsLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack

ADuC812

Parameter

Min

Typ

Max

Unit

SPI MASTER MODE TIMING (CPHA = 1)

SCLOCK Fall Time

Figure 56. SPI Master Mode Timing (CPHA = 1)