![](/images/new-backgrounds/1269281/269281103x1.webp)
ADuC812
Parameter |
| Min | Typ | Max | Unit | Figure |
|
|
|
|
|
| |
SPI MASTER MODE TIMING (CPHA = 1) |
|
|
|
|
| |
tSL | SCLOCK Low Pulsewidth |
| 330 |
| ns | 57 |
tSH | SCLOCK High Pulsewidth |
| 330 |
| ns | 57 |
tDAV | Data Output Valid after SCLOCK Edge |
|
| 50 | ns | 57 |
tDSU | Data Input Setup Time before SCLOCK Edge | 100 |
|
| ns | 57 |
tDHD | Data Input Hold Time after SCLOCK Edge | 100 |
|
| ns | 57 |
tDF | Data Output Fall Time |
| 10 | 25 | ns | 57 |
tDR | Data Output Rise Time |
| 10 | 25 | ns | 57 |
tSR | SCLOCK Rise Time |
| 10 | 25 | ns | 57 |
tSF | SCLOCK Fall Time |
| 10 | 25 | ns | 57 |
SCLOCK (CPOL=0)
SCLOCK (CPOL=1)
MOSI
MISO
tSH
tDAV
tSL
tDF
MSB
MSB IN
tSRtSF
tDR
BIT 6 – 1 | LSB |
BIT 6 – 1 | LSB IN |
tDSU tDHD
Figure 56. SPI Master Mode Timing (CPHA = 1)
REV. B |