Analog Devices ADuC812 - page 47

REV. B
ADuC812
–47–
12 MHz Variable Clock
Parameter Min Max Min Max Unit Figure
EXTERNAL PROGRAM MEMORY
t
LHLL
ALE Pulsewidth 127 2t
CK
–40 ns 52
t
AVLL
Address Valid to ALE Low 43 t
CK
–40 ns 52
t
LLAX
Address Hold after ALE Low 53 t
CK
–30 ns 52
t
LLIV
ALE Low to Valid Instruction In 234 4t
CK
– 100 ns 52
t
LLPL
ALE Low to PSEN Low 53 t
CK
–30 ns 52
t
PLPH
PSEN Pulsewidth 205 3 t
CK
–45 ns 52
t
PLIV
PSEN Low to Valid Instruction In 145 3t
CK
– 105 ns 52
t
PXIX
Input Instruction Hold after PSEN 00 ns52
t
PXIZ
Input Instruction Float after PSEN 59 t
CK
–25 ns 52
t
AVIV
Address to Valid Instruction In 312 5t
CK
– 105 ns 52
t
PLAZ
PSEN Low to Address Float 25 25 ns 52
t
PHAX
Address Hold after PSEN High 0 0 ns 52
MCLK
ALE (O)
PSEN (O)
PORT 0 (I/O)
PORT 2 (O)
tLHLL
tAVLL tLLPL tPLPH
tLLIV
tPLIV
tPLAZ
tLLAX tPXIX
tPXIZ
tPHAX
tAVIV
PCL (OUT) INSTRUCTION
(IN)
PCH
Figure 51. External Program Memory Read Cycle