ADuC812

 

 

12 MHz

 

Variable Clock

 

 

Parameter

 

Min

Max

Min

Max

Unit

Figure

 

 

 

 

 

 

 

EXTERNAL DATA MEMORY WRITE CYCLE

 

 

 

 

 

 

tWLWH

WR Pulsewidth

400

 

6tCK – 100

 

ns

54

tAVLL

Address Valid after ALE Low

43

 

tCK – 40

 

ns

54

tLLAX

Address Hold after ALE Low

48

 

tCK – 35

 

ns

54

tLLWL

ALE Low to RD or WR Low

200

300

3tCK – 50

3tCK + 50

ns

54

tAVWL

Address Valid to RD or WR Low

203

 

4tCK – 130

 

ns

54

tQVWX

Data Valid to WR Transition

33

 

tCK – 50

 

ns

54

tQVWH

Data Setup Before WR

433

 

7tCK – 150

 

ns

54

tWHQX

Data and Address Hold after WR

33

 

tCK – 50

 

ns

54

tWHLH

RD or WR High to ALE High

43

123

tCK – 40

6tCK – 100

ns

54

MCLK

 

 

ALE (O)

 

 

 

 

tWHLH

PSEN (O)

 

 

 

tLLWL

tWLWH

WR (O)

 

 

 

tAVWL

 

 

tQVWX

tWHQX

 

tLLAX

tQVWH

 

tAVLL

 

A0–A7

DATA

PORT 2 (O)

A16–A23

A8–A15

Figure 53. External Data Memory Write Cycle

REV. B

–49–

Page 49
Image 49
Analog Devices ADuC812 manual External Data Memory Write Cycle