Manuals / Analog Devices / Computer Equipment / Computer Hardware

Analog Devices ADuC812 manual Bit Name Description

Models: ADuC812

1 56

Download 56 pages 22.67 Kb

Page 10

ADuC812

OVERVIEW OF MCU-RELATED SFRs

Accumulator SFR

ACC is the Accumulator register and is used for math opera- tions including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for accumulator-specific instructions refer to the Accumulator as A.

B SFR

The B register is used with the ACC for multiplication and division operations. For other instructions it can be treated as a general-purpose scratchpad register.

Stack Pointer SFR

The SP register is the stack pointer and is used to hold an inter- nal RAM address that is called the “top of the stack.” The SP register is incremented before data is stored during PUSH and CALL executions. While the Stack may reside anywhere in on-chip RAM, the SP register is initialized to 07H after a reset. This causes the stack to begin at location 08H.

Data Pointer

The Data Pointer is made up of three 8-bit registers, named DPP (page byte), DPH (high byte) and DPL (low byte). These are used to provide memory addresses for internal and external code access and external data access. It may be manipulated as a 16-bit register (DPTR = DPH, DPL), although INC DPTR instructions will automatically carry over to DPP, or as three independent 8-bit registers (DPP, DPH, DPL).

Program Status Word SFR

The PSW register is the Program Status Word which contains several bits reflecting the current status of the CPU as detailed in Table I.

SFR Address

D0H

Power ON Default Value

00H

Bit Addressable

Yes

CY

AC

F0

RS1

RS0

OV

F1

P

Table I. PSW SFR Bit Designations

Bit

Name

Description

7

CY

Carry Flag

6

AC

Auxiliary Carry Flag

5

F0

General-Purpose Flag

4

RS1

Register Bank Select Bits

3

RS0

RS1

RS0

Selected Bank

0

0

0

0

1

1

1

0

2

1

1

3

2

OV

Overflow Flag

1

F1

General-Purpose Flag

0

P

Parity Bit

Power Control SFR

The Power Control (PCON) register contains bits for power- saving options and general-purpose status flags as shown in Table II.

SFR Address

87H

Power ON Default Value

00H

Bit Addressable

No

SMOD

ALEOFF

GF1

GF0

PD

IDL

Table II. PCON SFR Bit Designations

Bit

Name

Description

7

SMOD

Double UART Baud Rate

6

———

Reserved

5

———

Reserved

4

ALEOFF

Disable ALE Output

3

GF1

General-Purpose Flag Bit

2

GF0

General-Purpose Flag Bit

1

PD

Power-Down Mode Enable

0

IDL

Idle Mode Enable

–10–

REV. B

Image 10

Analog Devices ADuC812 manual Bit Name Description

Contents

Functional Block Diagram General DescriptionTable of Contents ADuC812Temperature SENSOR10 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 DAC Channel Specifications DC ACCURACY11Watchdog Timer Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Power Supply Monitor CharacteristicsIsource = 80 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 20 ∝APIN Configuration Temperature Package Model Range Description OptionOrdering Guide Mnemonic Type Function Terminology ADC SpecificationsDAC Specifications Thus for a 12-bit converter, this is 74 dBARCHITECTURE, Main Features Memory OrganizationBit Name Description Default Value SFR Address SFR Notes Special Function RegistersADC Transfer Function ADC Circuit InformationGeneral Overview Typical OperationAQ0 #ADC Clks EFHAQ1 ADCCON1.1 T2CCS3 CS2 CS1 CS0 CH# Location Name DescriptionBit Location Status Description Driving the A/D Converter Op Amp Model CharacteristicsTable VI. Some Single-Supply Op Amps ADC DMA Mode Configuring the ADCVoltage Reference Connections DMAP. Dmal must be written to first, followed by Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists Dmah and then by DmapByte Program Sequence SFR areaNonvolatile Flash Memory Eadrl EconB9H C6HCommand Byte Command Mode RNG1 FDHMode RNG0Using the D/A Converter Resistor String DAC Functional EquivalentSource and Sink Current Capability with Vref = VDD = 3 PRE1 PRE0 PRE2 C0HPRE2 WDR1CMP DFHDCH PsmiIspi F8HOOH WcolSPR1 SPR0 SPR1SPR0 F7HI2CCON 2C Control RegisterPin Alternate Function Compatible ON-CHIP PeripheralsTMOD, Tcon T2CONTF0 TF1TR1 TR0Mode 3 Two 8-Bit Timer/Counters TIMER/COUNTER 0 and 1 Operating ModesMode 1 16-Bit Timer/Counter EXF2 C8HTF2 RclkRclk or Tclk CAP2 TR2 ModeOFF SM0 SM1 SM0SM1 SM2Baud rate in Mode 0 is fixed CLK SmodRCAP2H RCAP2L ET2 A8HEadc ET1Source Priority Description Source Vector AddressClock Oscillator ADuC812 Hardware Design ConsiderationsExternal Memory Interface Level. The external POR circuit must be operational Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on High it tracks the voltage on DVDD. These recommendationsVDD = 5 VDD = 3 Normal ModeIdle Mode Core NAs ⋅ Mclk +Grounding and Board Layout Recommendations System Grounding SchemesOther Hardware Considerations In-Circuit Serial Download AccessEmbedded Serial Port Debugger Quickstart Development System ADSIM-Windows SimulatorXTAL1 Width High XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Rise Time12 MHz Variable Clock Parameter Min Max Unit External Program MemoryExternal Data Memory Read Cycle External Data Memory Write Cycle Serial Port Clock Cycle Time 12t CK Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Input Data Hold after ClockParameter Min Max Unit I2C-COMPATIBLE Interface TimingSPI Master Mode Timing Cpha = Parameter Min Typ Max UnitData Output Setup before Sclock Edge 150 SS to Sclock Edge SPI Slave Mode Timing Cpha =SS High after Sclock Edge Data Output Valid after SS Edge Location Data Sheet changed from REV. a to REV. B Entire Data Sheet has been revisedOutline Dimensions Lead Plastic Quad Flatpack