![](/images/new-backgrounds/1269281/26928195x1.webp)
ADuC812
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| 12 MHz |
| Variable Clock |
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Parameter |
| Min | Max | Min | Max | Unit | Figure |
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EXTERNAL DATA MEMORY READ CYCLE |
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tRLRH | RD Pulsewidth | 400 |
| 6tCK – 100 |
| ns | 53 |
tAVLL | Address Valid after ALE Low | 43 |
| tCK – 40 |
| ns | 53 |
tLLAX | Address Hold after ALE Low | 48 |
| tCK – 35 |
| ns | 53 |
tRLDV | RD Low to Valid Data In |
| 252 |
| 5tCK – 165 | ns | 53 |
tRHDX | Data and Address Hold after RD | 0 |
| 0 |
| ns | 53 |
tRHDZ | Data Float after RD |
| 97 |
| 2tCK | ns | 53 |
tLLDV | ALE Low to Valid Data In |
| 517 |
| 8tCK – 150 | ns | 53 |
tAVDV | Address to Valid Data In |
| 585 |
| 9tCK – 165 | ns | 53 |
tLLWL | ALE Low to RD or WR Low | 200 | 300 | 3tCK – 50 | 3tCK + 50 | ns | 53 |
tAVWL | Address Valid to RD or WR Low | 203 |
| 4tCK – 130 |
| ns | 53 |
tRLAZ | RD Low to Address Float |
| 0 |
| 0 | ns | 53 |
tWHLH | RD or WR High to ALE High | 43 | 123 | tCK – 40 | 6tCK – 100 | ns | 53 |
MCLK
ALE (O)
PSEN (O)
RD (O)
PORT 0 (I/O)
PORT 2 (O)
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| tWHLH |
| tLLDV |
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tLLWL |
| tRLRH |
tAVWL |
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| tRLDV | tRHDZ |
tLLAX |
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| tRHDX | |
tAVLL | tRLAZ | |
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| DATA (IN) | |
tAVDV |
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Figure 52. External Data Memory Read Cycle
REV. B |