![](/images/new-backgrounds/1269281/26928199x1.webp)
ADuC812
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| 12 MHz | Variable Clock |
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Parameter |
| Min Typ Max | Min | Typ | Max | Unit | Figure |
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UART TIMING (Shift Register Mode) |
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tXLXL | Serial Port Clock Cycle Time | 1.0 |
| 12tCK |
| ∝s | 55 |
tQVXH | Output Data Setup to Clock | 700 | 10tCK – 133 |
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| ns | 55 |
tDVXH | Input Data Setup to Clock | 300 | 2tCK + 133 |
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| ns | 55 |
tXHDX | Input Data Hold after Clock | 0 | 0 |
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| ns | 55 |
tXHQX | Output Data Hold after Clock | 50 | 2tCK – 117 |
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| ns | 55 |
ALE (O)
tXLXL
TxD | 0 | 1 | 6 | 7 | |
(OUTPUT CLOCK) |
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| tQVXH |
| SET RI | |
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| OR | ||
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| tXHQX | SET TI | |
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RxD | MSB | BIT6 | BIT1 | LSB | |
(OUTPUT DATA) |
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| tDVXH | tXHDX |
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RxD | MSB | BIT6 | BIT1 | LSB | |
(INPUT DATA) | |||||
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Figure 54. UART Timing in Shift Register Mode
REV. B |