Analog Devices ADuC812 manual ARCHITECTURE, Main Features, Memory Organization

ADuC812

ARCHITECTURE, MAIN FEATURES

The ADuC812 is a highly integrated true 12-bit data acquisition system. At its core, the ADuC812 incorporates a high- perfor- mance 8-bit (8052-Compatible) MCU with on-chip reprogrammable nonvolatile Flash program memory control- ling a multichannel (8-input channels), 12-bit ADC.

The chip incorporates all secondary functions to fully support the programmable data acquisition core. These secondary functions include User Flash Memory, Watchdog Timer (WDT), Power Supply Monitor (PSM) and various industry- standard parallel and serial interfaces.

PROGRAM MEMORY SPACE

READ ONLY

FFFFH

BANKS

SELECTED

VIA

BITS IN PSW

11

10

01

00

7FH

2FH

20H

1FH

18H

17H

10H

0FH

08H

07H

00H

BIT-ADDRESSABLE SPACE (BIT ADDRESSES 0FH–7FH)

4 BANKS OF 8 REGISTERS

R0–R7

RESET VALUE OF STACK POINTER

EXTERNAL

PROGRAM

MEMORY

SPACE

2000H
EA = 1	1FFFH
	EA = 0
INTERNAL	EXTERNAL
8K BYTE	PROGRAM
FLASH/EE	MEMORY
PROGRAM	SPACE
MEMORY	0000H

DATA MEMORY SPACE

READ/WRITE

Figure 2. Lower 128 Bytes of Internal RAM

MEMORY ORGANIZATION

As with all 8052-compatible devices, the ADuC812 has separate address spaces for Program and Data memory as shown in Fig- ure 1. Also as shown in Figure 1, an additional 640 Bytes of User Data Flash EEPROM are available to the user. The User Data Flash Memory area is accessed indirectly via a group of control registers mapped in the Special Function Register (SFR) area in the Data Memory Space.

The SFR space is mapped in the upper 128 bytes of internal data memory space. The SFR area is accessed by direct addressing only and provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADuC812 via the SFR area is shown in Figure 3.

9FH (PAGE 159)

640BYTES

FLASH/EE DATA

MEMORY

ACCESSED INDIRECTLY VIA SFR

CONTROL REGISTERS

00H		(PAGE 0)
		INTERNAL
		DATA MEMORY
		SPACE
	FFH			SPECIAL
		ACCESSIBLE		FUNCTION
		BY	REGISTERS
UPPER		INDIRECT	ACCESSIBLE
128		ADDRESSING		BY DIRECT
		ONLY	ADDRESSING
	80H			ONLY
	7FH	ACCESSIBLE
LOWER		BY
		DIRECT
128
		AND
		INDIRECT
		ADDRESSING

FFFFFFH

EXTERNAL

DATA

MEMORY

SPACE

FFH(24-BIT ADDRESS

SPACE)

80H

8K BYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE PROGRAM

MEMORY

	128-BYTE
8051	SPECIAL
	FUNCTION
COMPATIBLE
	REGISTER
CORE
	AREA

640-BYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE DATA

MEMORY

AUTO-CALIBRATING

8-CHANNEL

HIGH SPEED

12-BIT ADC

OTHER ON-CHIP

PERIPHERALS TEMPERATURE SENSOR

2 12-BIT DACs

SERIAL I/O

PARALLEL I/O

WDT

PSM

00H

000000H

Figure 3. Programming Model

Figure 1. Program and Data Memory Maps

The lower 128 bytes of internal data memory are mapped as shown in Figure 2. The lowest 32 bytes are grouped into four banks of eight registers addressed as R0 through R7. The next 16 bytes (128 bits) above the register banks form a block of bit addressable memory space at bit addresses 00H through 7FH.

REV. B –9–