Parameter Min Max Unit | Analog Devices ADuC812 instruction

ADuC812

Parameter		Min	Max	Unit	Figure

I2C-COMPATIBLE INTERFACE TIMING
tL	SCLOCK Low Pulsewidth	4.7		∝s	56
tH	SCLOCK High Pulsewidth	4.0		∝s	56
tSHD	Start Condition Hold Time	0.6		∝s	56
tDSU	Data Setup Time	100		ns	56
tDHD	Data Hold Time	0	0.9	∝s	56
tRSU	Setup Time for Repeated Start	0.6		∝s	56
tPSU	Stop Condition Setup Time	0.6		∝s	56
tBUF	Bus Free Time between a STOP			∝s
	Condition and a START Condition	1.3		∝s	56
tR	Rise Time of Both SCLOCK and SDATA		300	ns	56
tF	Fall Time of Both SCLOCK and SDATA		300	ns	56
1	Pulsewidth of Spike Suppressed		50	ns	56
tSUP	Pulsewidth of Spike Suppressed		50	ns	56

NOTE

1Input filtering on both the SCLOCK and SDATA inputs suppress noise spikes which are less than 50 ns.

tBUF

SDATA (I/O)

tDSU

tPSU

tSHD

SCLK (I)

STOP START

CONDITION CONDITION

MSB

tDHD

2-7

tSUP

LSB

tDSU

tSUP

ACK

tDHD

tRSU

S(R)

REPEATED

START

MSB

Figure 55. I2C-Compatible Interface Timing

REV. B

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Analog Devices ADuC812 manual Parameter Min Max Unit, I2C-COMPATIBLE Interface Timing

Contents

General Description Functional Block Diagram ADuC812 Table of Contents DAC Channel Specifications DC ACCURACY11 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 Temperature SENSOR10 Power Supply Monitor Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Watchdog Timer Characteristics Isource = 20 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 80 ∝A Temperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function Thus for a 12-bit converter, this is 74 dB ADC SpecificationsDAC Specifications Terminology Memory Organization ARCHITECTURE, Main Features Bit Name Description Special Function Registers Default Value SFR Address SFR Notes Typical Operation ADC Circuit InformationGeneral Overview ADC Transfer Function ADCCON1.1 T2C EFHAQ1 AQ0 #ADC Clks Location Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections Dmah and then by Dmap Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists DMAP. Dmal must be written to first, followed by SFR area Byte Program SequenceNonvolatile Flash Memory C6H EconB9H Eadrl Command Byte Command Mode RNG0 FDHMode RNG1 Resistor String DAC Functional Equivalent Using the D/A Converter Source and Sink Current Capability with Vref = VDD = 3 WDR1 C0HPRE2 PRE1 PRE0 PRE2 Psmi DFHDCH CMP Wcol F8HOOH Ispi F7H SPR1SPR0 SPR1 SPR0 2C Control Register I2CCON Compatible ON-CHIP Peripherals Pin Alternate Function T2CON TMOD, Tcon TR0 TF1TR1 TF0 TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter Rclk C8HTF2 EXF2 CAP2 TR2 Mode Rclk or TclkOFF SM2 SM0SM1 SM0 SM1 Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L ET1 A8HEadc ET2 Source Vector Address Source Priority Description ADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface High it tracks the voltage on DVDD. These recommendations Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on Level. The external POR circuit must be operational Core NAs ⋅ Mclk + Normal ModeIdle Mode VDD = 5 VDD = 3 System Grounding Schemes Grounding and Board Layout Recommendations In-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development System XTAL1 Rise Time XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Width High External Program Memory 12 MHz Variable Clock Parameter Min Max Unit External Data Memory Read Cycle External Data Memory Write Cycle Input Data Hold after Clock Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Serial Port Clock Cycle Time 12t CK I2C-COMPATIBLE Interface Timing Parameter Min Max Unit Parameter Min Typ Max Unit SPI Master Mode Timing Cpha = Data Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Lead Plastic Quad Flatpack Entire Data Sheet has been revisedOutline Dimensions Location Data Sheet changed from REV. a to REV. B

ADuC812

Parameter

Min

Max

Unit

I2C-COMPATIBLE INTERFACE TIMING

Figure 55. I2C-Compatible Interface Timing

REV. B