Freescale Semiconductor MC68HC08KH12 manual 103

PLLON — PLL On Bit

This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 8.4.8 Base Clock Selector Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.

1 = PLL on

0 = PLL off

BCS — Base Clock Select Bit

This read/write bit selects either the crystal oscillator clock (CGMXCLK) or the VCO clocks (CGMPCLK and CGMVCLK) to use as base clocks for the MCU.

BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMPCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. (See 8.4.8 Base Clock Selector Circuit.) Reset clears the BCS bit.

1 = Selects the VCO clocks for the base clock. CGMPCLK divided by two drives CGMOUT, CGMVCLK (48MHz) drives USBCLK

0 = Selects the crystal oscillator clock for the base clock. CGMXCLK divided by two drives CGMOUT, CGMXCLK drives USBCLK

NOTE: PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMPCLK/CGMVCLK requires two writes to the PLL control register. (See 8.4.8 Base Clock Selector Circuit.)

PRE1 and PRE0 — Pre scaler program bits

These read/write bits control a prescaler that selects the prescaler power-of-two multiplier P. (See 8.4.3 PLL Circuits and 8.4.6 Programming the PLL.) PRE1:PRE0 cannot be written when the PLLON bit is set. Reset clears these bits.

MC68HC(7)08KH12 — Rev. 1.1	Advance Information
Freescale Semiconductor	103