Freescale Semiconductor MC68HC08KH12 manual PIN Bit Set Timing, External Reset Timing

An internal reset clears the SIM counter (see 7.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the reset status register (RSR). (See 7.8 SIM Registers.)

7.4.1 External Pin Reset

The RST pin circuits include an internal pullup device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the reset status register (RSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that the POR was not the source of the reset. See Table 7-2for details. Figure 7-4shows the relative timing.

Table 7-2. PIN Bit Set Timing

Reset Type	Number of Cycles Required to Set PIN
POR	4163 (4096	+ 64 + 3)
All others	67 (64	+ 3)

CGMOUT

RST
IAB	PC	VECT H VECT L

Figure 7-4. External Reset Timing

7.4.2 Active Resets from Internal Sources

All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles. See Figure 7- 5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, or POR. (See Figure 7-6. Sources of Internal Reset.)

Note that for POR resets, the SIM cycles through 4096 CGMXCLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in

Figure 7-5.

MC68HC(7)08KH12 — Rev. 1.1	Advance Information
Freescale Semiconductor	67