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Freescale Semiconductor MC68HC08KH12 manual USB SIE Timing Status Register Sietsr, 125

Models: MC68HC08KH12

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SOFIE — Start Of Fr ame Interrupt Enable

This read/write bit enables the Start Of Frame to generate a USB interrupt when the SOFF bit becomes set. Reset clears this bit.

1 = USB interrupt enabled for Start Of Frame

0 = USB interrupt disabled for Start Of Frame

EOF2IE — The Second End of Fr ame Point Interrupt Enable

This read/write bit enables the Second End Of Frame to generate a USB interrupt when the EOF2F bit becomes set. Reset clears this bit. 1 = USB interrupt enabled for the Second End Of Frame Point

0 = USB interrupt disabled for the Second End Of Frame Point

EOPIE — End of Packet De tect Interrupt Enable

This read/write bit enables the USB to generate a interrupt request when the EOPF bit becomes set. Reset clears the bit.

1 = USB interrupt enabled for End-of-Packet sequence detection 0 = USB interrupt disabled for End-of-Packet sequence detection

TRANIE — Bus Signal Transitio n Detect Interrupt Enable

This read/write bit enables the Signal Transition to generate a USB interrupt when the TRANF bit becomes set. Reset clears this bit.

1 = USB interrupt enabled for Bus Signal Transition

0 = USB interrupt disabled for Bus Signal Transition

9.4.4 USB SIE Timing Status Register (SIETSR)

Address:	$0057
	Bit 7	6	5	4	3	2		1	Bit 0

Read:	RSTF	0	LOCKF	0	0	0		0	0
Write:
Write:		RSTFR		LOCKFR	SOFFR	EOF2FR		EOPFR	TRANFR

Reset:	0**	0	0	0	0	0		0	0
		= Unimplemented			0** = Reset by POR only
		= Unimplemented			0** = Reset by POR only

Figure 9-5. USB SIE Timing Status Register (SIETSR)

MC68HC(7)08KH12 — Rev. 1.1	Advance Information

Freescale Semiconductor	125

Image 125

Freescale Semiconductor MC68HC08KH12 manual USB SIE Timing Status Register Sietsr, 125

Contents

MC68HC08KH12 Data Sheet Page Advance Information MC68HC708KH12 List of SectionsPage Table of Contents Random-Access Memory RAM System Integration Module SIM Clock Generator Module CGM Universal Serial Bus Module USB Monitor ROM MON O Ports Computer Operating Properly COP Keyboard Interrupt Module KBI Break Module Break Mechanical Specifications Page Title List of FiguresHDP1CR-HDP4CR Title Title Title List of TablesTitle General Description ContentsIntroduction FeaturesPage 1shows the structure of the MC68HC708KH12 MCU Block DiagramMCU Block Diagram 2Shows the 64-pin QFP assignments Pin AssignmentsPower Supply Bypassing SIM Module KBI and . Timer Interface Module TIM. Page Advance Information MC68HC708KH12 Memory MapMemory Map I/O Section Control, Status, and Data Registers Toie Control, Status, and Data Registers Pllie Keyff Rxdie $FF8D $FFFF Vector Addresses Monitor ROM1is a list of vector locations Page This section describes the 384 bytes of RAM Random-Access Memory RAMFunctional Description Page Read-Only Memory ROM Page Configuration Register Config = COP module disabled = COP module enabled Configuration Register ConfigCentral Processor Unit CPU CPU Registers FeaturesCPU Registers Index Register HX Stack Pointer SP Program Counter PC Condition Code Register CCR Page Arithmetic/Logic Unit ALU Page Advance Information MC68HC708KH12 System Integration Module SIMIntroduction SIM Block Diagram SIM I/O Register Summary SIM Bus Clock Control and Generation 1shows the internal signal names used in this sectionSignal Name Conventions Reset and System Initialization PIN Bit Set Timing External Reset TimingPower-On Reset COP reset is asynchronous to the bus clockComputer Operating Properly COP Reset POR RecoveryUniversal Serial Bus Reset Illegal Opcode ResetIllegal Address Reset SIM Counter Exception Control Interrupt Processing Hardware Interrupts Interrupt Entry11.Interrupt Recognition Example Interrupt Sources SWI Instruction12. Interrupt Status Register 1 INT1 Interrupt Status Register14. Interrupt Status Register 2 INT2 13. Interrupt Status Register 2 INT2Low-Power Modes 15. Wait Mode Entry Timing 16. Wait Recovery from Interrupt or Break 18. Stop Mode Entry Timing SIM Registers SIM Registers21. Reset Status Register RSR 22. Break Flag Control Register Bfcr Page Advance Information MC68HC708KH12 Clock Generator Module CGMIntroduction 1shows the structure of the CGM CGM Block Diagram Page FRDV = fRCLK/R Page 3MHz, or 1.5MHz respectively Choose P = 0, 1, 2, or 3 for a bus frequency of 12MHz, 6MHzCGM Numeric Example Page CGM External Connections I/O Signals Cgmvsel CGM Registers 101 CGM I/O Register Summary102 PLL Control Register Pctl103 104 PRE10 Programming105 PLL Multiplier Select Registers PmshpmslRDS30 Reference Divider Select Bits Initializes the register to $01 for a default divide valueReference division factor R. See 8.4.3 PLL Circuits Programming the PLL. RDS70 cannot be written when107 InterruptsSpecial Modes 108 Acquisition/Lock Time Specifications109 110 111 112 113 Universal Serial Bus Module USB114 Features115 Overview116 I/O Register Description of the HUB function117 HUB Control Register Summary118 Setup119 HUB Data Register Summary120 USB HUB Root Port Control Register Hrpcr121 USB HUB Downstream Port Control Registers122 123 USB SIE Timing Interrupt Register Sietir124 125 USB SIE Timing Status Register Sietsr126 127 USB HUB Address Register Haddr128 USB HUB Interrupt Register 0 HIR0129 USB HUB Control Register 0 HCR0130 131 USB HUB Control Register 1 HCR1132 10. USB HUB Status Register HSR133 134 I/O Register Description of the Embedded Device Function135 Embedded Device Control Register Summary136 Embedded Device Data Register SummaryDE1D0 13713. USB Embedded Device Interrupt Register 0 DIR0 12. USB Embedded Device Address Register Daddr139 140 14. USB Embedded Device Interrupt Register 1 DIR1141 15. USB Embedded Device Control Register 0 DCR0142 143 16. USB Embedded Device Control Register 1 DCR1144 17. USB Embedded Device Status Register DSR145 146 18. USB Embedded Device Control Register 2 DCR2147 19. USB Embedded Device Endpoint 0 Data Register UE0D0-UE0D7148 20. USB Embedded Device Endpoint 0 Data Register UE0D0-UE0D7149 Monitor ROM MON150 Features151 Monitor Mode Circuit152 Mode Selection153 Mode DifferencesSample Monitor Waveforms Monitor Data Format155 Break Transaction156 Read Read Memory CommandWrite Write Memory Command 157 Iread Indexed Read CommandIwrite Indexed Write Command 158 Readsp Read Stack Pointer CommandRUN Run User Program Command 159 Monitor Baud Rate Selection160 161 Timer Interface Module TIM162 Introduction163 TIM Block Diagram164 TIM I/O Register Summary165 Buffered Output Compare Unbuffered Output CompareRegisters of the linked pair alternately control the output 166167 168 Unbuffered PWM Signal Generation169 Buffered PWM Signal Generation170 PWM InitializationTIM status control register TSC, clear the TIM stop bit 171 Wait Mode172 11.8 I/O SignalsTIM During Break Interrupts Minimum Tclk pulse width, Tclklmin or TCLKHMIN, is 11.9 I/O RegistersMaximum Tclk frequency is 173174 Resets the TIM counter Prescales the TIM counter clock175 Prescaler Selection176 TIM Counter Registers Tcnthtcntl177 TIM Counter Modulo Registers Tmodhtmodl178 TIM Channel Status and Control Registers TSC0TSC1179 See Table180 Mode, Edge, and Level Selection181 CHxMAX Latency182 TIM Channel Registers TCH0H/LTCH1H/L183 O Ports184 I/O Port Register Summary$0007 $0008 $0009 $000A $000B $001C $001D 185186 Port a3shows the port a I/O logic Data Direction Register a Ddra188 Port BPort a Pin Functions 6shows the port B I/O logic Data Direction Register B Ddrb190 Port CPort B Pin Functions 191 Data Direction Register C Ddrc192 Port DPort C Pin Functions 193 10. Port D Data Register PTD12shows the port D I/O logic 11. Data Direction Register D Ddrd195 Port EPort D Pin Functions 196 KBI15shows the port E I/O logic 14. Data Direction Register E Ddre198 Port E Pin FunctionsPTE0-PTE1 / PTE2-PTE3 199200 17. Optical Interface Voltage References201 18. Port E Optical Coupling Interface202 Port F3shows the port F I/O logic 20. Data Direction Register F Ddrf204 Port OptionsPort F Pin Functions 205 206 207 Computer Operating Properly COP1shows the structure of the COP module COP Block Diagram COP I/O Port Register Summary209 13.4 I/O Signals210 Configuration Register ConfigCOP Control Register Copctl Monitor ModeCOP does not generate CPU interrupt requests 211212 COP Module During Break Mode213 External Interrupt IRQIRQ module provides a non-maskable interrupt input 214 Functional Description215 IRQ Module Block Diagram IRQ I/O Port Register Summary216 217 IRQ Module During Break InterruptsIRQ Status and Control Register Iscr 218 219 Keyboard Interrupt Module KBI220 Introduction221 KBI I/O Register Summary222 Port-D Keyboard Interrupt Block Diagram223 224 225 Port-D Keyboard Status and Control Register226 Port-D Keyboard Interrupt Enable Register227 228 Port-E Keyboard Interrupt Block Diagram229 $FFED230 231 Port-E Keyboard Status and Control Register232 Port-E Keyboard Interrupt Enable Register233 234 Port-F Keyboard Interrupt Block Diagram235 236 237 Port-F Keyboard Status and Control Register238 Port-F Keyboard Interrupt Enable RegisterPort-F Pull-up Enable Register Stop ModeKeyboard Module During Break Interrupts 239240 241 Break Module Break242 Features243 Break Module Block Diagram Break I/O Register Summary244 Break Module Registers245 Break Status and Control Register Brkscr246 Break Address Registers Brkh and Brkl247 Preliminary Electrical Specifications248 Absolute Maximum Ratings249 Thermal CharacteristicsFunctional Operating Range 250 DC Electrical Characteristics251 Oscillator CharacteristicsControl Timing 252 USB DC Electrical Characteristics253 USB Low Speed Source Electrical Characteristics254 USB High Speed Source Electrical Characteristics255 HUB Repeater Electrical Characteristics256 USB Signaling LevelsTImer Interface Module Characteristics 257 Clock Generation Module Characteristics258 Acquisition/Lock Time Specifications259 Mechanical Specifications260 Plastic Quad Flat Pack QFPPage How to Reach Us