Advance Information MC68HC(7)08KH12 — Rev. 1.1
104 Freescale Semiconductor
8.6.2 PLL Bandwidth Control Register (PBWC)
The PLL bandwidth control register:
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
Since this CGM is optimized a frequency output of 48MHz for the USB
module, automatic control should be set. Reset clears the AUTO bit.
1 = Automatic bandwidth control (recommended)
0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
Table 8-3. PRE[1:0] Programming
PRE1 PRE0 P Prescaler Multiplier
000 1
011 2
102 4
113 8
Address: $003B
Bit 7654321Bit 0
Read:
AUTO
LOCK
ACQ
00000
Write:
Reset:00000000
= Unimplemented
Figure 8-4. PLL Bandwidth Control Register (PBWC)