Freescale Semiconductor MC68HC08KH12 manual CGM Numeric Example

2.Choose a practical PLL (crystal) reference frequency, fRCLK, and the reference clock divider, R.

Frequency errors to the PLL are corrected at a rate of fRCLK/R. For stability and lock time reduction, this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate. The relationship between the VCO frequency fVCLK and the reference frequency fRCLK is

2P ⋅ N( )

fVCLK = ----------------fRCLK R

2P ⋅ N( )

hence: 48MHz = ----------------fRCLK R

Choose the reference divider R = 1 for fast lock. Choose a fRCLK

frequency with an integer divisor of fBUS and solve for N.

3.Program the PLL registers accordingly:

a.In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P.

b.In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N.

c.In the PLL reference divider select register (PRDS), program the binary coded equivalent of R.

Table 8-1provides a numeric example (numbers are in hexadecimal notation):

Table 8-1. CGM Numeric Example

fBUS	fRCLK	P	N	R
6MHz	6MHz	1	004	1

8.4.7 Special Programming Exceptions

The programming method described in 8.4.6 Programming the PLL does not account for three possible exceptions. A value of zero for R, N, or L is meaningless when used in the equations given. To account for these exceptions:

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