Advance Information MC68HC(7)08KH12 — Rev. 1.1
88 Freescale Semiconductor
8.6.4 PLL Reference Divider Select Register (PRDS) . . . . . . . .106
8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.8.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.8.2 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .108
8.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .108
8.9.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . .108
8.9.2 Parametric Influences on Reaction Time . . . . . . . . . . . . .109
8.9.3 Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . .111
8.9.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . .111
8.2 Introduction
This section describes the clock generator module (CGM). The CGM
generates the crystal clock signal, CGMXCLK, which operates at the
frequency of the crystal. The CGM also generates the base clock signal,
CGMOUT, which is based on either the crystal clock divided by two or
the phase-locked loop (PLL) clock, CGMPCLK, divided by two. This is
the clock from which the SIM derives the system clocks, including the
bus clock, which is at a frequency of CGMOUT/2. The PLL also
generates a CGMVCLK clock, at 48MHz, for use as the USBCLK. The
PLL is a fully functional frequency generator designed for use with
crystals or ceramic resonators.
This CGM is optimized to generate a 48MHz reference frequency for the
USB module, from a 6MHz crystal.