Freescale Semiconductor MC68HC08KH12 manual 11.9 I/O Registers, Maximum Tclk frequency is, 173

minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is:

1	+ tSU
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bus frequency

The maximum TCLK frequency is:

bus frequency

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2

PTE0/TCLK is available as a general-purpose I/O pin when not used as the TIM clock input. When the PTE0/TCLK pin is the TIM clock input, it is an input regardless of the state of the DDRE0 bit in data direction register E.

11.8.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1)

Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTE1/TCH0 can be configured as buffered output compare or buffered PWM pins.

11.9 I/O Registers

The following I/O registers control and monitor operation of the TIM:

•TIM status and control register (TSC)

•TIM control registers (TCNTH:TCNTL)

•TIM counter modulo registers (TMODH:TMODL)

•TIM channel status and control registers (TSC0 and TSC1)

•TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)

11.9.1TIM Status and Control Register (TSC)

The TIM status and control register does the following:

•Enables TIM overflow interrupts

•Flags TIM overflows

•Stops the TIM counter

MC68HC(7)08KH12 — Rev. 1.1	Advance Information
Freescale Semiconductor	173