Freescale Semiconductor MC68HC08KH12 manual 216

•Vector fetch or software clear — A vector fetc h generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the ACK1 bit in the interrupt status and control register (ISCR).

The ACK1 bit is useful in applications that poll the IRQ1/VPP pin and require software to clear the IRQ1 latch. Writing to the ACK1

bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK1 does not affect

subsequent transitions on the IRQ1/VPP pin. A falling edge that occurs after writing to the ACK1 bit latches another interrupt

request. If the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB.

•Return of the IRQ1/VPP pin to logic one — As long as the IRQ1/VPP pin is at logic zero, IRQ1 remains active.

The vector fetch or software clear and the return of the IRQ1/VPP pin to logic one may occur in any order. The interrupt request remains pending as long as the IRQ1/VPP pin is at logic zero. A reset will clear the latch and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low.

If the MODE1 bit is clear, the IRQ1/VPP pin is falling-edge-sensitive only. With MODE1 clear, a vector fetch or software clear immediately clears the IRQ1 latch.

The IRQF1 bit in the ISCR register can be used to check for pending interrupts. The IRQF1 bit is not affected by the IMASK1 bit, which makes it useful in applications where polling is preferred.

Use the BIH or BIL instruction to read the logic level on the IRQ1/VPP pin.

NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine.

Advance Information	MC68HC(7)08KH12 — Rev. 1.1
216	Freescale Semiconductor