Freescale Semiconductor MC68HC08KH12 USB Signaling Levels, TImer Interface Module Characteristics

17.13 USB Signaling Levels

Bus State	Signaling Levels
	Transmit	Receive
Differential 1	D+ > VOH (min) and D– < VOL (max)	(D+) – (D–) > 200 mV
Differential 0	D– > VOH (min) and D– < VOL (max)	(D–) – (D+) > 200 mV
Single-ended 0 (SE0)	D+ and D– < VOL (max)	D+ and D– < VIL (max) (
Data J State
Low Speed	Differential 0	Differential 0
Full Speed	Differential 1	Differential 1
Data K State
Low Speed	Differential 1	Differential 1
Full Speed	Differential 0	Differential 0
Idle State		D– > VIHZ (min) and D+ < VIL (max)
Low Speed	NA
Full Speed		D+ > VIHZ (min) and D– < VIL (max)
Resume State	Data K State	Data K State
Start of Packet (SOP)	Data lines switch from Idle to K State
End of Packet (EOP)	SE0 for approximately 2 Bit Times(1)	SE0 for ≥ 1 Bit Times(2) followed by a J
	Followed by a J for 1 Bit Time
Reset	D+ and D– < VOL (max) for ≥10 ms	D+ and D– < VIL (max) for ≥ 2.5∝s

1.The width of EOP is defined in bit times relative to the speed of transmission.

2.The width of EOP is defined in bit times relative to the device type receiving the EOP. The bit time is approximate.

17.14 TImer Interface Module Characteristics

Characteristic	Symbol	Min	Max	Unit
Input Capture Pulse Width	tTIH, tTIL	125	—	ns
Input Clock Pulse Width	tTCH, tTCL	(1/fOP) + 5	—	ns

Advance Information	MC68HC(7)08KH12 — Rev. 1.1
256	Freescale Semiconductor