Freescale Semiconductor MC68HC08KH12 manual USB Embedded Device Interrupt Register 1 DIR1, 140

1 = Receive Embedded Device Endpoint 0 can generate a CPU interrupt request

0 = Receive Embedded Device Endpoint 0 cannot generate a CPU interrupt request

TXD0FR — Embedded Device En dpoint 0 Transmit Flag Reset

Writing a logic 1 to this write only bit will clear the TXD0F bit if it is set.

Writing a logic 0 to TXD0FR has no effect. Reset clears this bit.

RXD0FR — Embedded Device E ndpoint 0 Receive Flag Reset

Writing a logic 1 to this write only bit will clear the RXD0F bit if it is set.

Writing a logic 0 to RXD0FR has no effect. Reset clears this bit.

9.5.3 USB Embedded Device Interrupt Register 1 (DIR1)

Address:

Read:

Write:

Reset:

$004A
Bit 7	6	5	4	3	2	1	Bit 0
TXD1F	0	0	0	TXD1IE	0	0	0
						TXD1FR
0	0	0	0	0	0	0	0
	= Unimplemented

Figure 9-14. USB Embedded Device Interrupt Register 1 (DIR1)

TXD1F — Embedded Device Endpo int 1/2 Data Transmit Flag

This read only bit is shared by Endpoint 1 and Endpoint 2 of the embedded device. It is set after the data stored in the shared Endpoint 1/2 transmit buffer of the embedded device has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD1FR bit. To enable the next data packet transmission, TX1E must also be set. If TXD1F bit is not cleared, a NAK handshake will be returned in the next IN transaction. Reset clears this bit. Writing to TXD1F has no effect.

Advance Information	MC68HC(7)08KH12 — Rev. 1.1
140	Freescale Semiconductor