Freescale Semiconductor MC68HC08KH12 manual SIM Registers

7.8 SIM Registers

The SIM has three memory mapped registers. Table 7-4shows the

mapping of these registers.

Table 7-4. SIM Registers

Address	Register	Access Mode
$FE00	BSR	User
$FE01	RSR	User
$FE03	BFCR	User

7.8.1 Break Status Register (BSR)

The break status register contains a flag to indicate that a break caused an exit from stop or wait mode.

Address:

Read:

Write:

Reset:

$FE00
Bit 7	6	5	4	3	2	1	Bit 0
R	R	R	R	R	R	SBSW	R
						Note 1
						0
R	= Reserved			1. Writing a logic zero clears SBSW

Figure 7-20. Break Status Register (BSR)

SBSW — SIM Break Stop/Wait

This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW.

1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break

interrupt

SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this. Writing zero to the SBSW bit clears it.

MC68HC(7)08KH12 — Rev. 1.1	Advance Information
Freescale Semiconductor	83