12.3 Port A
Port A is an
12.3.1 Port A Data Register (PTA)
The port A data register contains a data latch for each of the eight port
A pins.
Address:
Read:
Write:
Reset:
$0000 |
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Bit 7 | 6 | 5 | 4 | 3 | 2 | 1 | Bit 0 |
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PTA7 | PTA6 | PTA5 | PTA4 | PTA3 | PTA2 | PTA1 | PTA0 |
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Unaffected by reset
Figure 12-1. Port A Data Register (PTA)
PTA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data.
The port A pullup enable bit, PAP, in the port option control register (POC) enables pullups on port A pins if the respective pin is configured as an input. (See 12.9 Port Options.)
12.3.2 Data Direction Register A (DDRA)
Data direction register A determines whether each port A pin is an input or an output. Writing a logic one to a DDRA bit enables the output buffer for the corresponding port A pin; a logic zero disables the output buffer.
Advance Information | MC68HC(7)08KH12 — Rev. 1.1 |
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186 | Freescale Semiconductor |
