Freescale Semiconductor MC68HC08KH12 - page 96

Advance Information MC68HC(7)08KH12 — Rev. 1.1
96 Freescale Semiconductor
A zero value for R or N is interpreted exactly the same as a value of one.
A zero value for L disables the PLL and prevents its selection as the
source for the base clock. (See 8.4.8 Base Clock Selector Circuit.)
8.4.8 Base Clock Selector Circuit
This circuit is used to select either the crystal clock, CGMXCLK, or the
PLL clock, CGMPCLK, as the source of the base clock, CGMOUT. The
two input clocks go through a transition control circuit that waits up to
three CGMXCLK cycles and three CGMPCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in
stasis. The output of the transition control circuit is then divided by two
to correct the duty cycle. Therefore, the bus clock frequency, which is
one-half of the base clock frequency, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMPCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the VCO clock.
This circuit is also used to select either the crystal clock, CGMXCLK or
the VCO clock, CGMVCLK, as the source of the USB clock, USBCLK.
8.4.9 CGM External Connections
In its typical configuration, the CGM requires seven external
components. Five of these are for the crystal oscillator and two are for
the PLL.
The crystal oscillator is normally connected in a Pierce oscillator
configuration, as shown in Figure 8-2. Figure 8-2 shows only the logical
representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:
• Crystal, X1
• Fixed capacitor, C1