Freescale Semiconductor MC68HC08KH12 - page 169

MC68HC(7)08KH12 — Rev. 1.1 Advance Information

Freescale Semiconductor 169

write a new, smaller pulse width value may cause the compare to be

missed. The TIM may pass the new value before it is written.

Use the following methods to synchronize unbuffered changes in the

PWM pulse width on channel x:

• When changing to a shorter pulse width, enable channel x output

compare interrupts and write the new value in the output compare

interrupt routine. The output compare interrupt occurs at the end

of the current pulse. The interrupt routine has until the end of the

PWM period to write the new value.

• When changing to a longer pulse width, enable channel x TIM

overflow interrupts and write the new value in the TIM overflow

interrupt routine. The TIM overflow interrupt occurs at the end of

the current PWM period. Writing a larger value in an output

compare interrupt routine (at the end of the current pulse) could

cause two output compares to occur in the same PWM period.

NOTE: In PWM signal generation, do not program the PWM channel to toggle

on output compare. Toggling on output compare prevents reliable 0%

duty cycle generation and removes the ability of the channel to

self-correct in the event of software error or noise. Toggling on output

compare also can cause incorrect PWM signal generation when

changing the PWM pulse width to a new, much larger value.

11.4.4.2 Buffered PWM Signal Generation

Channels 0 and 1 can be linked to form a buffered PWM channel whose

output appears on the PTE1/TCH0 pin. The TIM channel registers of the

linked pair alternately control the pulse width of the output.

Setting the MS0B bit in TIM channel 0 status and control register (TSC0)

links channel 0 and channel 1. The TIM channel 0 registers initially

control the pulse width on the PTE1/TCH0 pin. Writing to the TIM

channel 1 registers enables the TIM channel 1 registers to

synchronously control the pulse width at the beginning of the next PWM

period. At each subsequent overflow, the TIM channel registers (0 or 1)

that control the pulse width are the ones written to last. TSC0 controls

and monitors the buffered PWM function, and TIM channel 1 status and

Contents

Main Page List of Sections Page Table of Contents General Description Section 2. Memory Map Section 3. Random-Access Memory (RAM) Section 4. Read-Only Memory (ROM) Section 5. Configuration Register (CONFIG) Section 6. Central Processor Unit (CPU) Section 7. System Integration Module (SIM) Section 8. Clock Generator Module (CGM) Section 9. Universal Serial Bus Module (USB) Section 10. Monitor ROM (MON) Section 11. Timer Interface Module (TIM) Section 12. I/O Ports Section 13. Computer Operating Properly (COP) Section 14. External Interrupt (IRQ) Section 15. Keyboard Interrupt Module (KBI) Section 16. Break Module (BREAK) Section 17. Preliminary Electrical Specifications Section 18. Mechanical Specifications Page List of Figures Page Page Page List of Tables Page Section 1. General Description 1.1 Contents 1.2 Introduction 1.3 Features Page 1.4 MCU Block Diagram Figure 1-1. MCU Block Diagram 68HC(7)08KH12 28 1.5 Pin Assignments Figure 1-2. 64-Pin QFP Assignments (Top View) 1.5.1 Quad Flat Pack (QFP) Package Figure 1-2 Shows the 64-pin QFP assignments. Page Page Page Page Section 2. Memory Map 34 Figure 2-1. Memory Map 2.3 I/O Section 36 Figure 2-2. Control, Status, and Data Registers Page Page Page Page Page Page Table 2-1 is a list of vector locations. 2.4 Monitor ROM Table 2-1. Vector Addresses Page Section 3. Random-Access Memory (RAM) NOTE: 3.1 Contents 3.2 Introduction 3.3 Functional Description NOTE: Section 4. Read-Only Memory (ROM) Page Section 5. Configuration Register (CONFIG) 5.1 Contents 5.2 Introduction 5.3 Functional Description NOTE: Section 6. Central Processor Unit (CPU) 6.3 Features 6.4 CPU Registers Page Page Page Page Page NOTE: 6.5 Arithmetic/Logic Unit (ALU) Page Section 7. System Integration Module (SIM) 7.1 Contents 7.2 Introduction Figure 7-1. SIM Block Diagram 64 Figure 7-2. SIM I/O Register Summary 7.3 SIM Bus Clock Control and Generation 7.4 Reset and System Initialization Page Page Page Page 7.5 SIM Counter 7.6 Exception Control Figure 7-8. Interrupt Processing Page NOTE: Page Page 7.7 Low-Power Modes Page Page NOTE: 7.8 SIM Registers Page Page Page Section 8. Clock Generator Module (CGM) 8.1 Contents 8.2 Introduction 8.3 Features 8.4 Functional Description 90 PN Figure 8-1. CGM Block Diagram R Page Page Page Page a. b. c. Page Page 8.5 I/O Signals NOTE: Page 8.6 CGM Registers Table 8-2. CGM I/O Register Summary Page Page Page Page NOTE: 8.7 Interrupts NOTE: 8.8 Special Modes 8.9 Acquisition/Lock Time Specifications Page Page Page NOTE: Section 9. Universal Serial Bus Module (USB) 9.1 Contents 9.2 Features 9.3 Overview 12MHz 116 Figure 9-1. USB Block Diagram 9.4 I/O Register Description of the HUB function Table 9-1. HUB Control Register Summary Page Table 9-2. HUB Data Register Summary Page Page Page Page Page Page Page NOTE: Page Page Page Page Page Page 9.5 I/O Register Description of the Embedded Device Function Table 9-3. Embedded Device Control Register Summary 136 Table 9-4. Embedded Device Data Register Summary Page Page Page Page Page Page Page Page Page Page Page Page Section 10. Monitor ROM (MON) 10.3 Features 10.4 Functional Description Figure 10-1. Monitor Mode Circuit NOTE: Page Page Page 156 Table 10-3. READ (Read Memory) Command Table 10-4. WRITE (Write Memory) Command Table 10-5. IREAD (Indexed Read) Command Table 10-6. IWRITE (Indexed Write) Command Page Page Page Section 11. Timer Interface Module (TIM) 11.1 Contents 11.2 Introduction 11.3 Features 11.4 Functional Description Figure 11-1. TIM Block Diagram 164 Table 11-1. TIM I/O Register Summary Page Page Page Page Page NOTE: 11.5 Interrupts 11.6 Wait Mode 11.7 TIM During Break Interrupts 11.8 I/O Signals 11.9 I/O Registers Page Page Page Page Page Page NOTE: Page 182 Figure 11-8. TIM Channel Registers (TCH0H/L:TCH1H/L) Section 12. I/O Ports 12.1 Contents 184 12.2 Introduction NOTE: Page 12.3 Port A NOTE: 12.4 Port B NOTE: 12.5 Port C NOTE: 12.6 Port D Page NOTE: 12.7 Port E Page NOTE: Page Page 200 Figure 12-17. Optical Interface Voltage References Figure 12-18. Port E Optical Coupling Interface 12.8 Port F NOTE: 12.9 Port Options Page Page Section 13. Computer Operating Properly (COP) 13.1 Contents 13.2 Introduction 208 13.3 Functional Description Figure 13-1. COP Block Diagram Figure 13-1 shows the structure of the COP module. NOTE: 13.4 I/O Signals Page 13.5 COP Control Register (COPCTL) 13.6 Interrupts 13.7 Monitor Mode 13.8 Low-Power Modes 13.9 COP Module During Break Mode Section 14. External Interrupt (IRQ) 14.4 Functional Description NOTE: Freescale Semiconductor 215 Figure 14-1. IRQ Module Block Diagram Table 14-1. IRQ I/O Port Register Summary Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $001E IRQ Status/Control Register (ISCR) Read: 0000IRQF10 IMASK1 MODE1 Write: ACK1 Reset:00000000 = Unimplemented Page 14.5 IRQ Module During Break Interrupts 14.6 IRQ Status and Control Register (ISCR) Page Section 15. Keyboard Interrupt Module (KBI) 15.1 Contents 15.2 Introduction 15.3 Features Table 15-1. KBI I/O Register Summary 222 15.4 Port-D Keyboard Interrupt Block Diagram Figure 15-1. Port-D Keyboard Interrupt Block Diagram Page NOTE: Page Page Page 228 15.5 Port-E Keyboard Interrupt Block Diagram Figure 15-4. Port-E Keyboard Interrupt Block Diagram Page NOTE: Page Page Page 234 15.6 Port-F Keyboard Interrupt Block Diagram Figure 15-7. Port-F Keyboard Interrupt Block Diagram Page NOTE: Page Page 15.7 Wait Mode 15.8 Stop Mode 15.9 Keyboard Module During Break Interrupts Page Section 16. Break Module (BREAK) 16.1 Contents 16.2 Introduction 16.3 Features 16.4 Functional Description Figure 16-1. Break Module Block Diagram Table 16-1. Break I/O Register Summary 16.5 Break Module Registers Page 16.6 Low-Power Modes Section 17. Preliminary Electrical Specifications 17.1 Contents 17.2 Introduction 17.3 Absolute Maximum Ratings NOTE: 17.4 Functional Operating Range 17.5 Thermal Characteristics 17.6 DC Electrical Characteristics 17.7 Control Timing 17.8 Oscillator Characteristics 17.9 USB DC Electrical Characteristics 17.10 USB Low Speed Source Electrical Characteristics 17.11 USB High Speed Source Electrical Characteristics 17.12 HUB Repeater Electrical Characteristics Low Speed HUB Electrical Characteristics (Root port and downstream ports configured as low speed) Full Speed HUB Electrical Characteristics (Root port and downstream ports configured as full speed) 17.13 USB Signaling Levels 17.14 TImer Interface Module Characteristics 17.15 Clock Generation Module Characteristics 17.15.2 CGM Electrical Specifications 17.15.1 CGM Component Specifications 258 17.15.3 Acquisition/Lock Time Specifications Section 18. Mechanical Specifications 260 18.3 Plastic Quad Flat Pack (QFP) Figure 18-1. 64-Pin Quad-Flat-Pack (Case 840C-04) Page How to Reach Us: