When bit DDRBx is a logic one, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic zero, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table
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| Accesses to | Accesses to PTB | |
DDRB | PTB Bit |
| I/O Pin Mode | DDRB | ||
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| Read/Write | Read | Write | |
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0 | X(1) |
| Input, | DDRB[7:0] | Pin | PTB[7:0](3) |
1 | X |
| Output | DDRB[7:0] | PTB[7:0] | PTB[7:0] |
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1.X = don’t care
2.
3.Writing affects data register, but does not affect input.
12.5 Port C
Port C is a
12.5.1 Port C Data Register (PTC)
The port C data register contains a data latch for each of the five port C pins.
Address:
Read:
Write:
Reset:
$0002 |
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Bit 7 | 6 | 5 | 4 | 3 | 2 | 1 | Bit 0 |
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0 | 0 | 0 | PTC4 | PTC3 | PTC2 | PTC1 | PTC0 |
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Unaffected by reset
= Unimplemented
Figure 12-7. Port C Data Register (PTC)
Advance Information | MC68HC(7)08KH12 — Rev. 1.1 |
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190 | Freescale Semiconductor |