Freescale Semiconductor MC68HC08KH12 manual USB SIE Timing Interrupt Register Sietir, 123

SUSP1-SUSP4 — Downstream Po rt Selective Suspend Bit

This read/write bit forces the downstream port entering the selective suspend mode. This bit can be set by the host request SetPortFeature (PORT_SUSPEND) only. When this bit is set, the hub prevents propagating any bus activity (except the port reset or port resume request or the global reset signal) downstream, and the port can only reflect upstream bus state changes via the endpoint 1 of the hub. The blocking occurs at the next EOF2 point when this bit is set. Reset clears this bit.

1 = Force downstream port enters the selective suspend mode 0 = Default

D1+/D1– to D4+/D4– — Downs tream Port Differential Data

These read only bits are the differential data shown on the HUB downstream ports. When the bit SUSPND in the register HRPCR is 0, the data is the latched state at the last EOF2 sample point. When the bit SUSPND is 1, the data reflects the current state on the data line while accessing this register.

9.4.3 USB SIE Timing Interrupt Register (SIETIR)

Address:

Read:

Write:

Reset:

$0056
Bit 7	6	5	4	3	2	1	Bit 0
SOFF	EOF2F	EOPF	TRANF	SOFIE	EOF2IE	EOPIE	TRANIE
0	0	0	0	0	0	0	0
	= Unimplemented

Figure 9-4. USB SIE Timing Interrupt Register (SIETIR)

MC68HC(7)08KH12 — Rev. 1.1	Advance Information
Freescale Semiconductor	123