Freescale Semiconductor MC68HC08KH12 Data Direction Register B Ddrb, 6shows the port B I/O logic

12.4.2 Data Direction Register B (DDRB)

Data direction register B determines whether each port B pin is an input or an output. Writing a logic one to a DDRB bit enables the output buffer for the corresponding port B pin; a logic zero disables the output buffer.

Address:

Read:

Write:

Reset:

$0005
Bit 7	6	5	4	3	2	1	Bit 0
DDRB7	DDRB6	DDRB5	DDRB4	DDRB3	DDRB2	DDRB1	DDRB0
0	0	0	0	0	0	0	0

Figure 12-5. Data Direction Register B (DDRB)

DDRB[7:0] — Data Dire ction Register B Bits

These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs.

1 = Corresponding port B pin configured as output

0 = Corresponding port B pin configured as input

NOTE: Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1.

Figure 12-6shows the port B I/O logic.

INTERNAL DATA BUS

READ DDRB ($0005)

WRITE DDRB ($0005)

DDRBx

RESET

WRITE PTB ($0001)

PTBx

READ PTB ($0001)

PTBx

Figure 12-6. Port B I/O Circuit

MC68HC(7)08KH12 — Rev. 1.1	Advance Information
Freescale Semiconductor	189