Freescale Semiconductor MC68HC08KH12 manual SIM Bus Clock Control and Generation

Table 7-1shows the internal signal names used in this section.

	Table 7-1. Signal Name Conventions
Signal Name		Description
CGMXCLK		Buffered OSC1 from the oscillator
		The CGMXCLK frequency divided by two. This signal is again
CGMOUT		divided by two in the SIM to generate the internal bus clocks
		(Bus clock = CGMXCLK divided by four)
IAB		Internal address bus
IDB		Internal data bus
PORRST		Signal from the power-on reset module to the SIM
IRST		Internal reset signal
		Read/write signal
R/W

7.3 SIM Bus Clock Control and Generation

The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 7-3.

From	CGMXCLK	SIM COUNTER
PLL/OSCILLATOR
From	CGMOUT	⎟ 2	BUS CLOCK
PLL/OSCILLATOR			GENERATORS
			SIM

Figure 7-3. SIM Clock Signals

7.3.1 Bus Timing

In user mode, the internal bus frequency is the oscillator frequency (CGMXCLK) divided by four.

MC68HC(7)08KH12 — Rev. 1.1	Advance Information
Freescale Semiconductor	65