Table 12-2. Port A Pin Functions
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DDRA | PTA Bit | I/O Pin | to DDRA | |||
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Bit | Mode |
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| Read/Write | Read | Write | |||
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0 | X(1) | Input, | DDRA[7:0] | Pin | PTA[7:0](3) | |
1 | X | Output | DDRA[7:0] | PTA[7:0] | PTA[7:0] | |
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1.X = don’t care
2.
3.Writing affects data register, but does not affect input.
12.4 Port B
Port B is an
12.4.1 Port B Data Register (PTB)
The port B data register contains a data latch for each of the eight port B pins.
Address:
Read:
Write:
Reset:
$0001 |
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Bit 7 | 6 | 5 | 4 | 3 | 2 | 1 | Bit 0 |
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PTB7 | PTB6 | PTB5 | PTB4 | PTB3 | PTB2 | PTB1 | PTB0 |
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Unaffected by reset
Figure 12-4. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are
| The port B pullup enable bit, PBP, in the port option control register |
| (POC) enables pullups on port B pins if the respective pin is configured |
| as an input. (See 12.9 Port Options.). |
Advance Information | MC68HC(7)08KH12 — Rev. 1.1 |
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188 | Freescale Semiconductor |