Freescale Semiconductor MC68HC08KH12 manual USB HUB Root Port Control Register Hrpcr, 120

9.4.1 USB HUB Root Port Control Register (HRPCR)

Address:

Read:

Write:

Reset:

$005E
Bit 7	6	5	4	3	2	1	Bit 0
0	0	0	RESUM0	SUSPND	0	D0+	D0–
0	0	0	0	0	0	X	X
	= Unimplemented			X = Indeterminate

Figure 9-2. USB HUB Root Port Control Register (HRPCR)

RESUM0 — Force Resume to the Root Port

This read/write bit forces a resume signal (“K” state) onto the USB root port data lines to initiate a remote wakeup. Software should control the timing of the forced resume to be between 10 ms and 15 ms. Reset clears this bit.

1 = Force root port data lines to “K” state 0 = Default

SUSPND — USB Sus pend Control Bit

To save power, this read/write bit should be set by the software if at least 3ms constant idle state is detected on USB bus. Setting this bit puts the transceiver and regulator into a power savings mode.

This bit also determines the latch scheme for the data lines of the root port and the downstream port. When this bit is 1, the current state shown on the data lines will be reflected to the data register (D+/D–) directly. When the bit is 0, the data registers are the latched state sampled at the last EOF2 sample point. The hub repeater’s function is affected by this bit too. The upstream and downstream traffic will be blocked if this bit is set to 1. When the global resume or the downstream remote wakeup signal is found by the suspend hub, software is responsible to propagate the traffic between the root port and the enabled downstream port by setting the RESUMx control bit. Reset clears this bit.

Advance Information	MC68HC(7)08KH12 — Rev. 1.1
120	Freescale Semiconductor