MC68HC08KH12 Data Sheet
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List of Sections
Advance Information MC68HC708KH12
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Table of Contents
Random-Access Memory RAM
System Integration Module SIM
Clock Generator Module CGM
Universal Serial Bus Module USB
Monitor ROM MON
O Ports
Computer Operating Properly COP
Keyboard Interrupt Module KBI
Break Module Break
Mechanical Specifications
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List of Figures
Title
HDP1CR-HDP4CR
Title
Title
List of Tables
Title
Title
Contents
General Description
Features
Introduction
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MCU Block Diagram
1shows the structure of the MC68HC708KH12
MCU Block Diagram
Pin Assignments
2Shows the 64-pin QFP assignments
Power Supply Bypassing
SIM
Module KBI and . Timer Interface Module TIM.
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Memory Map
Memory Map
I/O Section
Control, Status, and Data Registers
Toie
Control, Status, and Data Registers
Pllie
Keyff
Rxdie
$FF8D $FFFF
Monitor ROM
1is a list of vector locations
Vector Addresses
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Random-Access Memory RAM
Functional Description
This section describes the 384 bytes of RAM
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Read-Only Memory ROM
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Configuration Register Config
Configuration Register Config
= COP module disabled = COP module enabled
Central Processor Unit CPU
CPU Registers
CPU Registers
Index Register HX
Stack Pointer SP
Program Counter PC
Condition Code Register CCR
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Arithmetic/Logic Unit ALU
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System Integration Module SIM
Introduction
SIM Block Diagram
SIM I/O Register Summary
1shows the internal signal names used in this section
Signal Name Conventions
SIM Bus Clock Control and Generation
Reset and System Initialization
External Reset Timing
PIN Bit Set Timing
COP reset is asynchronous to the bus clock
Power-On Reset
POR Recovery
Computer Operating Properly COP Reset
Illegal Opcode Reset
Illegal Address Reset
Universal Serial Bus Reset
SIM Counter
Exception Control
Interrupt Processing
Interrupt Entry
Hardware Interrupts
11.Interrupt Recognition Example
SWI Instruction
Interrupt Sources
Interrupt Status Register
12. Interrupt Status Register 1 INT1
13. Interrupt Status Register 2 INT2
14. Interrupt Status Register 2 INT2
Low-Power Modes
15. Wait Mode Entry Timing
16. Wait Recovery from Interrupt or Break
18. Stop Mode Entry Timing
SIM Registers
SIM Registers
21. Reset Status Register RSR
22. Break Flag Control Register Bfcr
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Clock Generator Module CGM
Introduction
1shows the structure of the CGM
CGM Block Diagram
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FRDV = fRCLK/R
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Choose P = 0, 1, 2, or 3 for a bus frequency of 12MHz, 6MHz
3MHz, or 1.5MHz respectively
CGM Numeric Example
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CGM External Connections
I/O Signals
Cgmvsel
CGM Registers
CGM I/O Register Summary
101
PLL Control Register Pctl
102
103
PRE10 Programming
104
PLL Multiplier Select Registers Pmshpmsl
105
Reference division factor R. See 8.4.3 PLL Circuits
Initializes the register to $01 for a default divide value
RDS30 Reference Divider Select Bits
Programming the PLL. RDS70 cannot be written when
Interrupts
Special Modes
107
Acquisition/Lock Time Specifications
108
109
110
111
112
Universal Serial Bus Module USB
113
114
Overview
115
I/O Register Description of the HUB function
116
HUB Control Register Summary
117
Setup
118
HUB Data Register Summary
119
USB HUB Root Port Control Register Hrpcr
120
USB HUB Downstream Port Control Registers
121
122
USB SIE Timing Interrupt Register Sietir
123
124
USB SIE Timing Status Register Sietsr
125
126
USB HUB Address Register Haddr
127
USB HUB Interrupt Register 0 HIR0
128
USB HUB Control Register 0 HCR0
129
130
USB HUB Control Register 1 HCR1
131
10. USB HUB Status Register HSR
132
133
I/O Register Description of the Embedded Device Function
134
Embedded Device Control Register Summary
135
Embedded Device Data Register Summary
136
137
DE1D0
12. USB Embedded Device Address Register Daddr
13. USB Embedded Device Interrupt Register 0 DIR0
139
14. USB Embedded Device Interrupt Register 1 DIR1
140
15. USB Embedded Device Control Register 0 DCR0
141
142
16. USB Embedded Device Control Register 1 DCR1
143
17. USB Embedded Device Status Register DSR
144
145
18. USB Embedded Device Control Register 2 DCR2
146
19. USB Embedded Device Endpoint 0 Data Register UE0D0-UE0D7
147
20. USB Embedded Device Endpoint 0 Data Register UE0D0-UE0D7
148
Monitor ROM MON
149
150
Monitor Mode Circuit
151
Mode Selection
152
Mode Differences
153
Monitor Data Format
Sample Monitor Waveforms
Break Transaction
155
Read Read Memory Command
Write Write Memory Command
156
Iread Indexed Read Command
Iwrite Indexed Write Command
157
Readsp Read Stack Pointer Command
RUN Run User Program Command
158
Monitor Baud Rate Selection
159
160
Timer Interface Module TIM
161
162
TIM Block Diagram
163
TIM I/O Register Summary
164
165
Registers of the linked pair alternately control the output
Unbuffered Output Compare
Buffered Output Compare
166
167
Unbuffered PWM Signal Generation
168
Buffered PWM Signal Generation
169
PWM Initialization
TIM status control register TSC, clear the TIM stop bit
170
Wait Mode
171
11.8 I/O Signals
TIM During Break Interrupts
172
Maximum Tclk frequency is
11.9 I/O Registers
Minimum Tclk pulse width, Tclklmin or TCLKHMIN, is
173
Resets the TIM counter Prescales the TIM counter clock
174
Prescaler Selection
175
TIM Counter Registers Tcnthtcntl
176
TIM Counter Modulo Registers Tmodhtmodl
177
TIM Channel Status and Control Registers TSC0TSC1
178
See Table
179
Mode, Edge, and Level Selection
180
CHxMAX Latency
181
TIM Channel Registers TCH0H/LTCH1H/L
182
O Ports
183
I/O Port Register Summary
184
185
$0007 $0008 $0009 $000A $000B $001C $001D
Port a
186
Data Direction Register a Ddra
3shows the port a I/O logic
Port B
Port a Pin Functions
188
Data Direction Register B Ddrb
6shows the port B I/O logic
Port C
Port B Pin Functions
190
Data Direction Register C Ddrc
191
Port D
Port C Pin Functions
192
10. Port D Data Register PTD
193
11. Data Direction Register D Ddrd
12shows the port D I/O logic
Port E
Port D Pin Functions
195
KBI
196
14. Data Direction Register E Ddre
15shows the port E I/O logic
Port E Pin Functions
198
199
PTE0-PTE1 / PTE2-PTE3
17. Optical Interface Voltage References
200
18. Port E Optical Coupling Interface
201
Port F
202
20. Data Direction Register F Ddrf
3shows the port F I/O logic
Port Options
Port F Pin Functions
204
205
206
Computer Operating Properly COP
207
COP Block Diagram COP I/O Port Register Summary
1shows the structure of the COP module
13.4 I/O Signals
209
210
COP does not generate CPU interrupt requests
Monitor Mode
COP Control Register Copctl
211
COP Module During Break Mode
212
External Interrupt IRQ
IRQ module provides a non-maskable interrupt input
213
214
IRQ Module Block Diagram IRQ I/O Port Register Summary
215
216
IRQ Module During Break Interrupts
IRQ Status and Control Register Iscr
217
218
Keyboard Interrupt Module KBI
219
220
KBI I/O Register Summary
221
Port-D Keyboard Interrupt Block Diagram
222
223
224
Port-D Keyboard Status and Control Register
225
Port-D Keyboard Interrupt Enable Register
226
227
Port-E Keyboard Interrupt Block Diagram
228
$FFED
229
230
Port-E Keyboard Status and Control Register
231
Port-E Keyboard Interrupt Enable Register
232
233
Port-F Keyboard Interrupt Block Diagram
234
235
236
Port-F Keyboard Status and Control Register
237
Port-F Keyboard Interrupt Enable Register
238
Keyboard Module During Break Interrupts
Stop Mode
Port-F Pull-up Enable Register
239
240
Break Module Break
241
242
Break Module Block Diagram Break I/O Register Summary
243
Break Module Registers
244
Break Status and Control Register Brkscr
245
Break Address Registers Brkh and Brkl
246
Preliminary Electrical Specifications
247
Absolute Maximum Ratings
248
Thermal Characteristics
Functional Operating Range
249
DC Electrical Characteristics
250
Oscillator Characteristics
Control Timing
251
USB DC Electrical Characteristics
252
USB Low Speed Source Electrical Characteristics
253
USB High Speed Source Electrical Characteristics
254
HUB Repeater Electrical Characteristics
255
USB Signaling Levels
TImer Interface Module Characteristics
256
Clock Generation Module Characteristics
257
Acquisition/Lock Time Specifications
258
Mechanical Specifications
259
Plastic Quad Flat Pack QFP
260
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