Freescale Semiconductor MC68HC08KH12 manual PWM Initialization, 170

control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, PTE2/TCH1, is available as a general-purpose I/O pin.

NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered PWM signals.

11.4.4.3 PWM Initialization

To ensure correct operation when generating unbuffered or buffered

PWM signals, use the following initialization procedure:

	1. In the TIM status and control register (TSC):
	a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
	b. Reset the TIM counter by setting the TIM reset bit, TRST.
	2. In the TIM counter modulo registers (TMODH:TMODL), write the
	value for the required PWM period.
	3. In the TIM channel x registers (TCHxH:TCHxL), write the value for
	the required pulse width.
	4. In TIM channel x status and control register (TSCx):
	a. Write 0:1 (for unbuffered output compare or PWM signals) or
	1:0 (for buffered output compare or PWM signals) to the mode
	select bits, MSxB:MSxA. (See Table 11-3.)
	b. Write 1 to the toggle-on-overflow bit, TOVx.
	c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
	compare) to the edge/level select bits, ELSxB:ELSxA. The
	output action on compare must force the output to the
	complement of the pulse width level. (See Table 11-3.)
NOTE:	In PWM signal generation, do not program the PWM channel to toggle
	on output compare. Toggling on output compare prevents reliable 0%
	duty cycle generation and removes the ability of the channel to
	self-correct in the event of software error or noise. Toggling on output
	compare can also cause incorrect PWM signal generation when
	changing the PWM pulse width to a new, much larger value.
	5. In the TIM status control register (TSC), clear the TIM stop bit,
	TSTOP.
Advance Information	MC68HC(7)08KH12 — Rev. 1.1
170	Freescale Semiconductor