12.2 Introduction
I/O pins are programmable as inputs or outputs.
NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage.
Table 12-1. I/O Port Register Summary
Addr.Register Name
$0000 | Port A Data Register | |
(PTA) | ||
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$0001 | Port B Data Register | |
(PTB) | ||
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$0002 | Port C Data Register | |
(PTC) | ||
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$0003 | Port D Data Register | |
(PTD) | ||
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$0004 | Data Direction Register A | |
(DDRA) | ||
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$0005 | Data Direction Register B | |
(DDRB) | ||
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$0006 | Data Direction Register C | |
(DDRC) | ||
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| Bit 7 | 6 | 5 | 4 | 3 | 2 | 1 | Bit 0 | |
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Read: | PTA7 | PTA6 | PTA5 | PTA4 | PTA3 | PTA2 | PTA1 | PTA0 | |
Write: | |||||||||
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Reset: |
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| Unaffected by reset |
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Read: | PTB7 | PTB6 | PTB5 | PTB4 | PTB3 | PTB2 | PTB1 | PTB0 | |
Write: | |||||||||
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Reset: |
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| Unaffected by reset |
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Read: | 0 | 0 | 0 | PTC4 | PTC3 | PTC2 | PTC1 | PTC0 | |
Write: |
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Reset: |
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| Unaffected by reset |
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Read: | PTD7 | PTD6 | PTD5 | PTD4 | PTD3 | PTD2 | PTD1 | PTD0 | |
Write: | |||||||||
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Reset: |
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| Unaffected by reset |
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Read: | DDRA7 | DDRA6 | DDRA5 | DDRA4 | DDRA3 | DDRA2 | DDRA1 | DDRA0 | |
Write: | |||||||||
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Reset: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
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Read: | DDRB7 | DDRB6 | DDRB5 | DDRB4 | DDRB3 | DDRB2 | DDRB1 | DDRB0 | |
Write: | |||||||||
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Reset: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
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Read: | 0 | 0 | 0 | DDRC4 | DDRC3 | DDRC2 | DDRC1 | DDRC0 | |
Write: |
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Reset: | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Advance Information | MC68HC(7)08KH12 — Rev. 1.1 |
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184 | Freescale Semiconductor |