Freescale Semiconductor MC68HC08KH12 manual 112

an initial frequency error, (fDES – fORIG)/fDES, of not more than ±100 percent.

 VDDA  8  tACQ =  ------------  ------------

fRDV KACQ

 VDDA  4  tAL =  ------------  -----------

fRDV KTRK

tLOCKMAX = tACQ + tAL + 256tVRDV

NOTE: The inverse proportionality between the lock time and the reference frequency.

In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. (See 8.4.5 Manual and Automatic PLL Bandwidth Modes.) A certain number of clock cycles, nACQ, is required to ascertain that the PLL is within the tracking mode entry tolerance, ∆TRK, before exiting acquisition mode. A certain number of clock cycles, nTRK, is required to ascertain that the PLL is within the lock mode entry tolerance, ∆LOCK. Therefore, the acquisition

time, tACQ, is an integer multiple of nACQ/fRDV, and the acquisition to lock time, tAL, is an integer multiple of nTRK/fRDV.

In manual mode, it is usually necessary to wait considerably longer than

tLOCKMAX before selecting the PLL clock (See 8.4.8 Base Clock Selector Circuit.), because the factors described in 8.9.2 Parametric

Influences on Reaction Time may slow the lock time considerably.

Automatic bandwidth mode is recommended for most users.

Advance Information	MC68HC(7)08KH12 — Rev. 1.1
112	Freescale Semiconductor