Freescale Semiconductor MC68HC08KH12 Data Direction Register D Ddrd, 12shows the port D I/O logic

Address:

Read:

Write:

Reset:

$0007
Bit 7	6	5	4	3	2	1	Bit 0
DDRD7	DDRD6	DDRD5	DDRD4	DDRD3	DDRD2	DDRD1	DDRD0
0	0	0	0	0	0	0	0

Figure 12-11. Data Direction Register D (DDRD)

DDRD[7:0] — Data Dire ction Register D Bits

These read/write bits control port D data direction. Reset clears DDRD[7:0], configuring all port D pins as inputs.

1 = Corresponding port D pin configured as output

0 = Corresponding port D pin configured as input

NOTE: Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1.

Figure 12-12shows the port D I/O logic.

INTERNAL DATA BUS

READ DDRD ($0007)

WRITE DDRD ($0007)

DDRDx

RESET

WRITE PTD ($0003)

PTDx

READ PTD ($0003)

PTDx

Figure 12-12. Port D I/O Circuit

When bit DDRDx is a logic one, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic zero, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 12-5summarizes the operation of the port D pins.

Advance Information	MC68HC(7)08KH12 — Rev. 1.1
194	Freescale Semiconductor