Technical Reference Guide
4.3AGP BUS OVERVIEW
NOTE: For a detailed description of AGP bus operations refer to the AGP Interface Specification Rev. 2.0 available at the following AGP forum web site: http://www.agpforum.org/index.htm
The Accelerated Graphics Port (AGP) bus is specifically designed as an economical yet high- performance interface for graphics adapters, especially those designed for 3D operations. The AGP interface is designed to give graphics adapters dedicated pipelined access to system memory for the purpose of
4.3.1 BUS TRANSACTIONS
The operation of the AGP bus is based on the
Key differences between the AGP interface and the PCI interface are as follows:
♦Address phase and associated data transfer phase are disconnected transactions. Addressing and data transferring occur as contiguous actions on the PCI bus. On the AGP bus a request for data and the transfer of data may be separated by other operations.
♦Commands on the AGP bus specify system memory accesses only. Unlike the PCI bus, commands involving I/O and configuration are not required or allowed. The system memory address space used in AGP operations is the same linear space used by PCI memory space commands, but is further specified by the graphics address
♦Data transactions on the AGP bus involve eight bytes or multiples of eight bytes. The AGP memory addressing protocol uses
♦Pipelined requests are defined by length or size on the AGP bus. The PCI bus defines transfer lengths with the FRAME- signal.
There are two basic types of transactions on the AGP bus: data requests (addressing) and data transfers. These actions are separate from each other.
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Featuring the AMD Athlon XP Processor
Second Edition - April 2003